RF Power Amplifier PCB Floorplanning: Heat and Return Paths

AMPLIFIER DESIGN / BEFORE THE FIRST RF TRACE

RF power amplifier PCB floorplanning should start with the package, cooling attachment and return paths, then place the RF interfaces and bias network around those constraints. A short signal route is useful only when its reference conductor, supply loop and heat-removal path also work. Reserve the mechanical and test interfaces before filling the remaining board area.

This guide produces a placement-review worksheet, not a ready-to-build amplifier. The worked example uses an invented 10 W continuous operating point to show how a heat budget can change a floorplan. It is separate from the published device example below. No thermal simulation, RF stability analysis or physical test was performed for these illustrations.

1. Freeze the interfaces that placement cannot repair

Start the drawing with four boundaries: RF input and output reference planes; all supply rails entering the amplifier; the surface connected to the cooling system; and the mechanical envelope. Record the intended frequency band, waveform, output power and permitted distortion at a defined operating point. “10 W amplifier” alone does not say whether that means average power, peak power or a saturated single-tone result.

For each connector, reserve its land pattern, edge clearance, mounting hardware and mating-cable access. For the device, reserve the manufacturer’s package footprint and exposed-pad region. For the cooling attachment, reserve contact area, fasteners, electrical clearances and assembly access. A screw hole added after routing can remove precisely the reference copper or thermal area the design relies on.

Use a short placement record with named owners: RF engineering approves the signal interfaces; the power designer approves bias and sequencing; mechanical engineering approves the cooling contact; manufacturing confirms the proposed assembly. The RF amplifier application review connects those requirements to fabrication and acceptance planning.

2. Map RF, bias and heat on the same floorplan

Draw three overlays before detailed routing. The RF overlay connects input, matching elements where required, the active device and output. The bias overlay shows the supply entry, local storage, device supply pins and the corresponding return. The thermal overlay follows heat through the package attachment to the eventual cooling surface. Separate colors help reviewers identify an interface that appears in one overlay but is missing from another.

A practical first arrangement keeps the input and output interfaces on opposite sides of the amplifier region, with the bias entry on a third side. This is a starting hypothesis, not a spacing rule. If the enclosure forces both RF connectors onto one edge, document the resulting parallel routing and evaluate its coupling rather than labeling the original placement rule “satisfied.”

Analog Devices’ RF and mixed-signal layout guidance identifies long adjacent RF routes, interrupted reference planes and shared supply paths as issues to examine. Keep the RF reference continuous under the intended transmission structure. Partition component functions through placement without automatically cutting the ground plane between them.

In the review, trace a complete return for every highlighted route. At a layer change, identify how the reference current changes layers. At an output connector, check both the center conductor and its ground connection. Mark any proposed shield or ground-via fence as a structure to model and manufacture; neither its presence nor a chosen pitch proves stability or isolation.

3. Turn the operating point into a cooling-space requirement

Use watts at one consistent amplifier boundary. Power-added efficiency is η_PAE = (P_out − P_in)/P_DC, as defined in the Analog Devices PAE reference. Include the relevant supply rails and state whether support circuits are outside that boundary. Do not combine output power at a cable end with input power at a device pin without accounting for the intervening losses.

For this illustrative continuous-wave worksheet, assume P_out = 10 W, P_in = 0.10 W and η_PAE = 0.40. These are selected teaching inputs, not specifications for a named device. Power conservation gives:

P_DC = (10 − 0.10)/0.40 = 24.75 W
P_heat = P_DC + P_in − P_out = 14.85 W

That heat must leave the modeled amplifier boundary. The drain-efficiency ratio P_out/P_DC is approximately 40.40%, whereas PAE is 40.00%. Reproduce both values in the application page’s power tool using 0.10 W input, 10 W output and 24.75 W DC. Its output deliberately does not predict temperature.

Now select a 125°C junction design target, a 55°C cooling-surface temperature and a hypothetical junction-to-case resistance of 3°C/W. These are additional worksheet assumptions, not an ADPA1106 rating. In a simplified steady-state series path carrying all 14.85 W to that surface:

θ_total,max = (125 − 55)/14.85 = 4.714°C/W
θ_{board+interfaces,max} = 4.714 − 3 = 1.714°C/W

The 30% row leaves almost no resistance for the board and attachment. That should trigger a review of the assumed operating point, device and cooling arrangement before artwork release. It does not establish that adding copper will meet the target. Reserve a larger contact region or consider a different heat path only after checking the associated electrical and mechanical constraints.

Analog Devices’ AN-1604, revision 0, explains package-to-board-to-heatsink thermal networks and dissipation accounting. An actual assembly has spreading, contact and parallel heat-flow effects; package thermal parameters also depend on their stated conditions. Replace this worksheet’s assumed resistance with a justified model and validate the assembled boundary conditions.

Build the layer-function map before routing. Use the interactive stackup library to copy a concept construction, then annotate the RF reference layer, bias distribution, exposed-pad connection and cooling interface. Its nominal thickness total is not a thermal result or a released stackup.

4. Learn from a real evaluation board without copying its limits

The ADPA1106-EVALZ provides a concrete interface example. UG-2037, revision 0, April 2022, describes a two-layer board made from 10 mil Rogers 4350B copper clad, supported by an aluminum heat spreader. It uses 50 Ω grounded coplanar RF traces, ground connections beneath the package and a separate through-calibration route. Those details show why the electrical, mechanical and measurement drawings belong together.

They do not authorize using its footprint, bias or cooling assumptions for another PA. The ADPA1106 data sheet, revision A, explicitly requires pulsed operation and reports thermal behavior for stated pulse conditions. The continuous 10 W arithmetic above is not an operating recommendation for that part. Obtain the exact device revision and operating restrictions before transferring any evaluation-board practice.

5. Reserve the bias loop and assembly process

Place the local bypass network as a complete loop: device supply connection, capacitor, ground connection and return to the device. In the placement record, identify the loop’s physical route instead of recording only a distance between component centers. Keep bulk storage, filtering, gate control and monitoring distinguishable so a later layout change cannot silently combine their paths.

Capacitance values alone do not define bypass performance. Murata’s decoupling and loop-impedance guidance explains the roles of connection inductance and antiresonance between parallel capacitors. Review the mounted network over the relevant spectrum using the selected components’ models. A bank of different capacitor values is not automatically broadband decoupling.

Document how the bias system enters its allowed states during startup, shutdown, loss of control and a fault. Follow the selected PA’s sequencing instructions; a generic gate/drain order is not a substitute. Leave accessible monitoring points for supply voltage at the device boundary and current measurement without forcing a long probe connection through the RF input area.

The exposed pad and via arrangement also need an assembly decision. Texas Instruments’ QFN and SON attachment guide, SLUA271C, December 2023, discusses solder-volume loss through vias and process tradeoffs for plugging or tenting. Use it as packaging context, not as the land pattern for an unrelated RF device. Agree the actual hole structure, pad finish, stencil and inspection criteria with the assembler.

The copper and thermal construction review helps organize these fabrication questions. A resin-filled via, a solder-filled via and a copper-filled structure are different specifications. Do not allow a drawing label such as “thermal vias” to leave the filling, capping or attachment assumptions implicit.

6. Make the prototype answer specific questions

Reserve measurement access before approving the outline. List the question, test boundary, operating state and evidence required. The following plan is a starting checklist to adapt to the selected amplifier and available instruments; it does not claim any board has passed.

• RF path: define input/output reference planes, cable and fixture corrections, load conditions, gain, output power and application-specific distortion limits. Select attenuators, couplers and loads with appropriate ratings.
• Bias behavior: observe startup, steady operation and commanded transitions. Record rail voltages and current with the waveform and timing settings. Resolve overshoot or unexpected current before interpreting an RF result.
• Thermal boundary: measure the specified cooling surface and accessible package or board locations under documented mounting, airflow and power conditions. Record stabilization criteria. An infrared surface image is not a direct junction-temperature measurement.
• Coupling and stability: investigate unexpected tones or response changes across the agreed operating and load range. Retain the shield, enclosure and cable configuration; do not turn a single successful bench setup into an unconditional stability claim.
• Assembly: retain the stackup revision, via construction, component substitutions and agreed solder-joint inspection records so a thermal or RF change can be traced to a physical build.

For pulsed or modulated operation, preserve the timing and averaging definitions in the report. Average dissipation alone cannot establish peak junction temperature. Compare the chosen transient model and operating restrictions with the actual waveform. Keep these records alongside the fabrication-note release checklist so prototype findings become controlled manufacturing inputs.

Sources reviewed October 14, 2026. Figures are original engineering concepts and calculations, not product photographs or measured performance. Device-specific documentation and the approved fabrication, assembly and test package control the actual build.