PCB Quarter-Wave Transformer Design: A 10 GHz Worked Example

MICROWAVE DESIGN / A MATCHING NETWORK YOU CAN CHECK

A PCB quarter-wave transformer matches two real impedances at a chosen frequency when its characteristic impedance is their geometric mean and its electrical length is 90 degrees. On a microstrip board, physical length depends on effective permittivity, while width depends on the stackup. Neither dimension is ready for fabrication until copper, transitions, tolerances and test interfaces have been reviewed.

This worked example connects a 50 Ω system to a purely resistive 100 Ω load at 10 GHz. It starts with documented RO4003C material data and ends with a validation plan. The method also applies to other suitable laminates after replacing the material and construction model. All numerical results below are original ideal calculations, not EM simulations, measurements or a guaranteed product design.

1. Define the load at the correct reference plane

Write down the impedance to be matched, its frequency dependence and the physical plane where it is defined. A component data-sheet impedance at a package pin is not automatically the impedance at the far side of a footprint, via or feed line. For an antenna, installation and feed geometry also belong in the load definition.

For real positive source resistance R_S and load resistance R_L, the ideal transformer impedance is Z_T = √(R_SR_L). At exactly one quarter guided wavelength, Z_in = Z_T²/R_L. Thus √(50 × 100) = 70.7107 Ω, and the input becomes 50 Ω. The operating principle and real-load restriction are described in Keysight’s Matching Network Yin-Yang, Part 2, publication 5989-9012.

If the load is 100 + j30 Ω, substituting 100 into that equation discards a requirement. Transform or compensate the reactance, or select a different matching topology and evaluate its bandwidth. Also keep impedance transformation separate from galvanic isolation: this continuous printed transmission line does not provide the isolation associated with some wound transformers.

2. Translate material data into a line model

The example assumes an isolated outer-layer microstrip over an uninterrupted ground plane, with air above the trace. Its nominal dielectric height h is 0.008 inch, converted exactly to 0.2032 mm. Copper thickness is deliberately zero in the first calculation; a real foil and finished copper thickness must be added in the subsequent production model.

The Rogers RO4000 data sheet, publication 92-004, revision 1592 080322, lists RO4003C design Dk as 3.55 using the differential phase length method over 8–40 GHz. It separately gives process Dk 3.38 ±0.05 at 10 GHz and 23°C using clamped stripline. Page 4 lists the nominal 0.008-inch construction. These quantities are not interchangeable; this example uses 3.55 as a modeling input, not as a guaranteed value for every delivered board.

Effective permittivity ε_eff describes the modeled field shared between air and substrate. It changes with width-to-height ratio and is lower than the substrate input in this microstrip model. The existing microstrip impedance and width solver uses the zero-thickness Hammerstad–Jensen approximation. Its model reference is the Qucs single-microstrip documentation, equations 11.4, 11.6 and 11.15–11.18.

To reproduce the geometry, select “Solve width for target impedance,” enter ε_r = 3.55, h = 0.2032 mm and target 70.710678 Ω, then calculate. The result is W/h ≈ 1.2174, W ≈ 0.2474 mm and ε_eff ≈ 2.6631. Save the copied result with its assumptions. It represents an initial mathematical width, not an etch-compensated drawing dimension.

3. Calculate length using effective permittivity

For a lossless, nondispersive first model, guided wavelength is λ_g = c/(f√ε_eff), and transformer length is ℓ = λ_g/4. Here c = 299,792,458 m/s, frequency f is in hertz and length is in meters before conversion to millimeters. At 10 GHz, the example gives λ_g ≈ 18.3709 mm and ℓ ≈ 4.5927 mm.

Putting the substrate value 3.55 directly into the wavelength equation would instead give about 3.9778 mm. That is a different field model. Using the 50 Ω feed’s effective permittivity is another avoidable error: the feed and transformer have different widths, so this model gives different effective permittivities for them.

A 100 Ω load does not require a long 100 Ω trace. The third row only shows what that additional line would mean in the same ideal geometry. Any such line moves the physical interface and must be included in the network.

Check the phase before routing. In the electrical length explorer, enter 10 GHz, effective permittivity 2.66307131 and route length 4.592713 mm. It returns approximately 90° and 25 ps. That confirms the arithmetic; it does not validate a connector or width step.

4. Check bandwidth instead of only the center-frequency match

Keep the same ideal real load and constant line parameters while sweeping frequency. A numerically convenient input-impedance equation is:

Z_in = Z_T(R_L cos θ + jZ_T sin θ)/(Z_T cos θ + jR_L sin θ)
θ = 2πfℓ√ε_eff/c
Γ = (Z_in − 50)/(Z_in + 50); return loss = −20 log₁₀|Γ|

θ is in radians and j is the imaginary unit. The sine/cosine form avoids evaluating tan θ at its quarter-wave singularity. Reflected power fraction is |Γ|², not |Γ|. With no dissipative loss in this model, accepted power fraction is 1 − |Γ|²; a physical board also dissipates and may radiate power.

At 8 and 12 GHz, calculated return loss is 19.28 dB and reflected power is about 1.18%. At 9 and 11 GHz, the values are 25.16 dB and 0.305%. At 10 GHz, reflection is mathematically zero. Consequently, an illustrative requirement of at least 20 dB across 8–12 GHz already fails at the edges in this ideal model. Do not spend layout effort trying to rescue a topology without first checking its required band.

Loss, dispersive material behavior and a frequency-dependent load break the simplified symmetry. A lossy board can show a less dramatic reflection while delivering less useful power. Evaluate transmission and dissipated power alongside matching rather than treating a low S11 trace as the entire acceptance test.

5. Replace ideal junctions with the manufactured layout

The width change from the 50 Ω feed to the transformer is a discontinuity. A load pad, bend, nearby ground pour, solder fillet or connector launch can add further reactive behavior. Preserve straight-line dimensions as named variables, and model the actual transitions instead of assuming that every extra feature belongs inside an ideal 90° section.

A connected matching section is not an open-ended resonator. Do not subtract an open-end correction from both ends by default. Use discontinuity models appropriate to the topology, then a suitable EM model for the combined geometry. If top-side ground becomes electrically significant, the structure is no longer the isolated microstrip used in the worksheet.

For the next model, enter finished copper thickness and profile, mask coverage, finish, dielectric thickness, the documented material model and surrounding conductors. Sweep width and length separately before combining process variations. As a phase-only illustration, changing the 4.5927 mm length by ±0.10 mm moves the ideal 90° frequency to approximately 9.787 or 10.223 GHz. This selected sweep is not a factory tolerance or a prediction of the actual return-loss minimum.

6. Design the measurement around the intended load

A common validation mistake is to attach both ends directly to 50 Ω VNA ports and expect the same matching result as a 100 Ω termination. In the ideal example at 10 GHz, terminating the transformer in 50 Ω makes its input 100 Ω. The corresponding input return loss is only 9.54 dB. That result does not contradict the intended 50-to-100 Ω transformation.

One option is a one-port input-reflection test with the intended load installed and characterized at the specified output plane. A nominal 100 Ω resistor is not necessarily 100 + j0 Ω at 10 GHz; include its package, pads and ground connection. Another option is a full two-port characterization followed by fixture removal and network analysis with the intended load. Renormalization changes the mathematical port reference; it does not physically replace a termination or remove a fixture.

Keysight’s E5072A fixture-simulator documentation separates network de-embedding from impedance conversion. Its PLTS reference-plane guidance also distinguishes simple port extension from de-embedding with an accurate fixture model. Choose the method that fits the hardware and retain the calibration record.

7. Release a reviewable fabrication and test package

Before requesting the prototype, close these items with the design and manufacturing teams:

• Network: frequency band, source/load impedances, their reference planes, power and permitted reflection or transmission limits.
• Construction: exact laminate grade, core thickness, copper option, layer/reference assignment, mask and finish, plus permitted alternatives.
• Geometry: transformer width and length, transition and pad dimensions, surrounding ground and any tuning variants.
• Evidence: model version and assumptions, tolerance sweep, measurement fixture, calibration/de-embedding method and load characterization.
• Release control: one fabrication revision, agreed inspection scope and approval for any material or artwork change affecting the RF network.

The RF PCB design review guide organizes the wider handoff. For the underlying relationship between physical trace length and propagation, the trace-delay worksheet provides complementary examples. Neither a checklist nor a nominal impedance coupon establishes the complete matching-network response.

Sources reviewed October 13, 2026. Figures are original engineering illustrations and calculations. No full-wave simulation or physical measurement was performed for this article; final dimensions require construction-specific verification.