PCB Transmission Line Rise Time: A Delay Worksheet

RF ENGINEERING / EDGE RATE AND PROPAGATION DELAY

For PCB transmission-line screening, compare the trace’s one-way propagation delay with the fastest relevant rise or fall time—not simply the clock frequency. A useful conservative starting point is to investigate distributed behavior when delay reaches about one-sixth of the edge time. This is a screening guideline, not a physical boundary or a guarantee that shorter traces work. The driver, load, topology and permitted waveform error determine the final decision.

Every interconnect has distributed inductance and capacitance. What changes is whether a lumped approximation adequately represents your circuit. This worksheet helps identify nets that need a transmission-line model before layout release. It applies to digital control and clock nets on RF and mixed-signal boards; a separate phase calculation below addresses sinusoidal RF paths. For the wider release process, use the RF PCB design guide.

1. Record the edge that actually launches into the route

A 10 MHz clock has a 100 ns period, but its output may switch in a small fraction of a nanosecond. Slowing the repetition rate does not necessarily slow that transition. TI’s High-Speed Layout Guidelines, SCAA082A, revised August 2017, explains the relationship between edge rate and a digital waveform’s higher-frequency content. Check the selected output drive and slew settings, not just the bus-rate label.

Write down both rise and fall times, measurement thresholds, supply, load, temperature and model revision. Use the faster applicable transition for initial screening. A maximum rise-time specification describes the slow end of a limit; it does not establish the fastest edge you might encounter. If the required minimum or waveform information is missing, mark that input as unknown and request a suitable vendor model.

Do not silently mix 10–90% and 20–80% values. TI’s SLYT413 IBIS application article, 2Q 2011, pages 7 and 9, gives a one-sixth lumped-circuit criterion and explains that IBIS [Ramp] data uses a 20–80% interval with a stated load. A simple conversion assumes a waveform shape; it is not universally exact. Keep the definition with the value and use the appropriate loaded waveform for detailed analysis.

2. Calculate one-way delay with explicit units

For an approximately uniform, low-loss, quasi-TEM line with negligible dispersion over the range being considered:

v = c / √ε_eff
t_d = L / v = L√ε_eff / c
r = t_d / t_edge

Here L is routed length in millimetres, c = 299.792458 mm/ns, ε_eff is dimensionless effective relative permittivity, v is velocity in mm/ns, and both times are in ns. The ratio r is dimensionless. Count meanders in the route length. For a path containing different line sections, add their individual delays; model connectors, packages and vias separately where a uniform-line approximation is inadequate.

Effective permittivity describes the field distribution of the transmission structure. It is not automatically the substrate datasheet Dk. Microstrip fields occupy both dielectric and air, while a homogeneous stripline has a different field environment. Analog Devices’ Clock Skew in Large Multi-GHz Clock Trees, equations 1–2, relates delay to length and effective permittivity and discusses differences between line types. Preserve the actual construction and model assumptions.

For all examples here, ε_eff = 3.0 is an assumed teaching value, not a claim for any laminate. It gives v ≈ 173.1 mm/ns and delay ≈ 5.778 ps/mm. The construction qualification worksheet explains what material and stackup evidence to collect before replacing this assumption with a project model.

3. Apply the worksheet to three routing decisions

The table uses assumed 10–90% edge times and the same idealized effective permittivity. Values are calculated, rounded examples; they are neither oscilloscope results nor simulation output.

Example A: at 10 MHz, the 100 ns clock period might make an 80 mm connection appear harmless. However, its 0.462 ns flight time is almost the assumed 0.50 ns edge time. A wave reflected at the far end takes approximately 0.924 ns to travel out and back along this ideal line. Whether that reflection causes an unacceptable crossing depends on the endpoints and their behavior.

Example B: keeping the route unchanged while increasing the edge time to 5 ns reduces the ratio tenfold. This could support a simpler initial model, provided the receiver accepts that slew and timing. Selecting a slower drive mode is a design change that needs verification, not an automatic repair. A heavily loaded node can still settle too slowly even when line delay is small.

Example C: shortening the fast-edge route to 30 mm helps, but it remains above the one-sixth screen. Solve the same relation for a screening length: L_screen = vt_edge/6 ≈ 14.4 mm for 0.50 ns and ε_eff = 3.0. This number is a trigger for closer analysis, not a universal maximum PCB trace length.

4. Treat different rules of thumb as different screens

Analog Devices’ MT-097, Dealing with High Speed Logic, Rev. 0, January 2009, presents a guideline for transmission-line treatment when one-way delay reaches half the fastest rise or fall time. That is less conservative than the one-sixth criterion used above. Both are engineering shortcuts with context; neither replaces a permitted-error requirement.

State which criterion you used so reviewers do not compare incompatible “critical lengths.” A result between the two thresholds is a reason to inspect the circuit, not to select whichever rule approves the artwork. A sensitive sampling-clock input and a tolerant status input can have different consequences from the same distortion. Record the actual voltage and timing limits at the receiver.

Build a reviewable starting point: use the microstrip impedance and width solver for its stated isolated, uncoated, zero-thickness model. Save its inputs and effective permittivity with this worksheet. It does not calculate receiver ringing, model differential or coplanar routes, or qualify a production stackup.

5. Use phase length for a sinusoidal RF path

A continuous RF tone does not have a digital rise time to enter into this worksheet. For the same idealized uniform line, calculate its phase length: θ = 360ft_d, with θ in degrees and compatible frequency/time units. Using GHz with ns is convenient. The phase delay depends on frequency and geometry; a dispersive path requires a frequency-dependent model.

At 2.4 GHz, a 10 mm line with assumed ε_eff = 3.0 has t_d ≈ 0.0578 ns and θ ≈ 49.9°. It is not an electrically negligible connection in a phase-sensitive network, even though the same length might pass a slow digital-edge screen. Choose acceptable phase error from the circuit requirement. Do not convert the digital one-sixth guideline into an antenna, matching-network or filter rule.

6. Separate line geometry from termination decisions

Controlled geometry establishes a target characteristic impedance. Termination concerns how the source and load interact with that line. A uniform 50 Ω route does not by itself make an arbitrary digital interface matched, and 50 Ω is not a compulsory target for every signal. Start with the interface and device requirements, then evaluate the implemented topology.

For a simple point-to-point connection, a source-series resistor can be a candidate when the driver’s output impedance is lower than the line impedance. The driver impedance counts as part of the termination. MT-097 discusses this arrangement and its limitations. Branches, multiple receivers and intermediate sampling points require their own analysis. Keep candidate damping components near the relevant source and check both rising and falling behavior with the actual models.

A useful simulation comparison changes one variable at a time: original route, shorter route, supported slew setting, then a candidate termination. Keep the receiver model and acceptance limits fixed. Capture the complete topology so a “better” endpoint waveform has not concealed an unacceptable intermediate node or a setup-and-hold violation.

7. Release a testable manufacturing and validation record

Use the controlled-impedance manufacturing review to turn the proposed net class into an agreed build and acceptance plan. Include these items with the board revision:

• Electrical definition: driver and receiver part numbers, model versions, supply/temperature corners, edge definitions, drive settings and critical net names.
• Physical path: layer and reference plane, routed length, stackup, finished copper, mask, branches, vias, connectors and any restricted geometry.
• Fabrication agreement: target impedance, tolerance, representative coupon, test method, reporting requirements and approval rules for artwork changes.
• Receiver acceptance: operating voltage limits, overshoot/undershoot limits where specified, allowed settling, threshold crossings, setup/hold and jitter requirements.

Plan the measurements before placing test pads. Record probe type, loading, attachment, bandwidth, fixture and measurement location. Compare the receiver waveform with the defined limits across relevant operating conditions. A long probe ground connection or an added test stub can change the very behavior being investigated. Label all plots as measured or simulated and retain their settings and board revision.

A coupon impedance result addresses the agreed fabrication structure. It does not prove that an assembled clock reaches every receiver correctly. Keep coupon results and circuit validation together, with an owner for unresolved differences. Repeat the affected checks when the driver, stackup, topology or firmware-controlled slew changes.

Discuss a measurable RF PCB validation plan. Send your operating band or interface rate, fastest edge information, transmission geometry, reference planes, proposed stackup and acceptance limits through the project review and quotation form. Identify missing inputs explicitly so the review can separate a geometry estimate from the simulation and testing still required.

Technical references checked 8 October 2026. Numerical examples and diagrams are original calculations under stated assumptions, not material specifications, certified limits or measured board results.