TDR Impedance Test Report | Sample & Interpretation

What a TDR Impedance Test Report Actually Tells You

A TDR impedance test report documents the characteristic impedance of controlled-impedance traces on a PCB, measured by launching a fast-rise-time step into a dedicated test coupon and recording the reflected voltage over time. The report converts that reflection into an impedance-versus-distance profile so you can verify that every controlled net falls within its specified tolerance—typically ±10 % for single-ended lines and ±10 % for differential pairs, though RF designs often tighten this to ±5 % or even ±3 %. If you have never read one of these reports before, the next few sections walk through every field, waveform feature, and failure scenario you are likely to encounter.

How TDR Measurement Works—A 60-Second Primer

Time-domain reflectometry sends an electrical step with a rise time between 20 ps and 200 ps down a transmission line. At every point where the impedance changes, a fraction of the step reflects back. The instrument plots reflected voltage against round-trip propagation time, which it converts to distance using the known velocity of propagation (Vp) of the dielectric. For a 50 Ω microstrip on RO4350B (Dk 3.48, Vp ≈ 0.54 c), one nanosecond of round-trip time corresponds to roughly 81 mm (3.2 in) of physical trace length. A deeper explanation of the measurement physics is covered in the TDR measurement basics guide.

Modern TDR instruments—such as the Tektronix DSA8300 or Keysight N1930B Physical Layer Test System—offer effective rise times down to 9 ps, giving spatial resolution better than 0.5 mm. For standard PCB acceptance testing, a 35 ps system rise time is more than adequate to resolve coupon traces that are 150 mm (6 in) or longer.

Anatomy of a TDR Impedance Test Report

A complete report contains header information, tabulated impedance readings, and the waveform screenshots. Here is what each section means.

Header Block

• Job / lot number – ties the report to a specific production lot.
• Board part number and revision – must match your Gerber release.
• Date of test and operator ID – for material traceability and audit trail.
• Instrument model, serial number, and calibration due date – if the cal date is past, the report is invalid.
• Reference standard – usually IPC-TM-650 method 2.5.5.7 for characteristic impedance by TDR.

Impedance Data Table

The table is the first thing most engineers check. A typical layout looks like this:

Each row corresponds to a coupon trace. A well-designed coupon set includes at least one trace per controlled-impedance class per signal layer. The “measured” value is typically the average impedance across the flat region of the waveform, excluding launch and termination artifacts. When impedance testing is specified, every row must pass for the lot to ship.

Waveform Screenshots

The waveform is the most information-rich part of the report, yet it is the part most engineers skip. Each screenshot shows impedance (Y-axis, in ohms) versus distance or time (X-axis). Key features to look for:

• Launch region – the first 5–10 mm where the SMA connector or probe tip transitions into the coupon trace. Expect a brief impedance spike or dip here; it is not part of the trace measurement.
• Flat region – the stable plateau representing the true characteristic impedance of the trace. The flatter this region, the more uniform the etch and dielectric thickness are.
• Ripple – periodic impedance undulations (±1–2 Ω) usually indicate glass-weave effects in the laminate, especially on thin cores with spread-glass styles like 1067 or 1078.
• End reflection – the open-circuit rise at the far end of the coupon. Its position confirms the coupon length and Vp.

Tolerance Windows: How Tight Is Tight Enough?

IPC-6012 Class 2 calls for ±10 % on single-ended and ±10 % on differential impedance. Class 3 (military/aerospace) uses the same default, but most procurement specs override it. In RF and microwave work, ±5 % is standard, and some 77 GHz radar and mmWave 5G designs call for ±3 %. Tightening the window below ±5 % has real cost implications: the fabricator must hold copper etch tolerance to ±0.5 mil (≈ 13 µm) and dielectric thickness to ±0.5 mil, which limits the choice of high-frequency laminate and press cycle.

When reviewing a report, always verify that the tolerance stated on the report matches your drawing note. A common disconnect: the fabricator tests to ±10 % (their default) while the drawing calls for ±7 %. The coupon may “pass” the report yet violate your specification.

Common Failure Modes and Root Causes

Impedance Reads High (Trace Too Narrow or Dielectric Too Thick)

If every trace on a given layer reads 3–8 % above target, the most likely causes are over-etching (trace narrower than artwork) or a pressed dielectric thickness that exceeds the stackup model. A cross-section analysis of the same panel will confirm which dimension drifted.

Impedance Reads Low (Trace Too Wide or Dielectric Too Thin)

The mirror case: under-etching or thinner-than-modeled prepreg. On hybrid stackups mixing FR-4 prepreg with PTFE cores, resin flow during lamination can thin the dielectric unpredictably.

Impedance Slope Along the Trace

A waveform that ramps steadily from 48 Ω at the launch end to 53 Ω at the open end points to a taper in etch uniformity across the panel—common on large panels etched in conveyorized spray systems where leading and trailing edges see different dwell times.

Localized Impedance Dip or Spike

A sudden dip of 5 Ω or more at a specific point along the trace suggests a physical defect: a copper nick, a via stub coupling into the trace, or a foreign-object inclusion in the dielectric. Correlate the time-domain position to a physical location on the coupon and inspect visually or with X-ray.

When a Coupon Fails: The 8D Corrective-Action Path

A failed TDR impedance test should trigger a structured corrective-action process. Many OEMs require the fabricator to file an 8D report documenting the root cause, containment actions, and long-term corrective measures. Use the tool below to start building an 8D framework around an impedance failure—enter the failure description, affected lot, and interim containment action to generate a structured starting document.

For example, if coupon SE-L6-75 fails at 71.1 Ω against a 75 Ω ±5 % window (lower limit 71.25 Ω), the 8D containment might be: hold all panels from the same press load, cross-section two panels to measure actual dielectric thickness, and re-etch a replacement lot with adjusted imaging compensation. The long-term corrective action could involve updating the stackup model’s prepreg thickness assumption based on measured post-lamination data rather than datasheet nominals.

Complementary Tests That Strengthen a TDR Report

A TDR impedance test confirms Z₀ at DC-equivalent frequencies (the bandwidth is set by the step rise time, roughly 0.35/t_r). It does not directly measure insertion loss, which matters just as much for signal integrity above a few GHz. Pairing TDR with a VNA insertion loss test gives a complete picture: impedance accuracy plus frequency-dependent attenuation. For loss-sensitive designs, the Delta-L test method offers a faster loss-screening alternative using the same coupon set.

Surface Finish and Environmental Durability

Surface finish affects the probe-to-pad contact resistance during TDR measurement and the long-term reliability of the board. ENIG, immersion silver, and OSP are common; each has different shelf-life and solderability characteristics. When a product must survive harsh environments—marine, automotive underhood, outdoor base stations—salt spray testing per ASTM B117 or IPC-TM-650 2.6.15 is often required alongside impedance verification. Use the selector below to determine which salt spray test duration and acceptance criteria apply to your finish and application class.

A typical result: ENIG finish tested for 48 hours with no base-metal corrosion visible at 10× magnification passes most commercial requirements. Military programs may extend this to 96 or 168 hours. If your TDR coupon also serves as a salt-spray witness coupon, make sure the surface finish on the coupon matches the production boards—some fabricators default coupon pads to bare copper, which will give misleading corrosion results.

Best Practices for Reviewing a TDR Report

1. Match the spec. Confirm the tolerance on the report matches your drawing note, not the fabricator’s default.
2. Check calibration. The instrument cal date must be current. A 50 Ω cal standard verified to ±0.2 Ω is typical for IEEE-traceable measurements.
3. Read the waveforms. A passing number from a noisy or sloped waveform deserves a question. Ask for the raw data file (.wfm or .csv) if the screenshot is unclear.
4. Verify coupon-to-board correlation. The coupon must be on the same panel, same press load, and same etch run as the production boards. A coupon from a different lot is meaningless.
5. Cross-reference with cross-section. If impedance is marginal (within 1 % of the limit), request a cross-section to confirm copper width and dielectric thickness are within the stackup model.
6. Archive the report. For first article inspection, the TDR report is a mandatory deliverable. Store it with the lot traveler for full traceability.

Frequently Asked Questions

What rise time should the TDR use for PCB impedance testing?

A system rise time of 35–50 ps is standard for production acceptance testing per IPC-TM-650 2.5.5.7. Faster rise times (9–20 ps) resolve finer discontinuities but may flag features—like via anti-pads—that do not affect real-world performance, increasing false-fail rates.

Can TDR measure differential impedance directly?

Yes. A differential TDR module drives odd-mode and even-mode steps simultaneously into both lines of a pair and reports Zdiff (odd-mode) and Zcomm (even-mode). Most modern instruments display both in a single acquisition.

How many coupons per panel are needed?

IPC-6012 requires at least one impedance coupon per impedance class per panel. Best practice for RF boards is two coupons per class—one at each end of the panel—to catch etch uniformity gradients.

Does TDR impedance testing replace S-parameter verification?

No. TDR characterizes impedance (Z₀) and qualitative discontinuities. S-parameter measurement on a VNA gives insertion loss (S21), return loss (S11), and phase across frequency. Both are needed for a complete RF acceptance package.

Is a TDR impedance test destructive?

Not to the production board—testing is performed on sacrificial coupons that share the panel but are routed away before shipment. The coupon itself is not damaged and can be retested or archived.