KiCad RF Design Workflow | Free Tools for Layout

Can You Do Serious RF Design in KiCad?

Yes. KiCad 8.x handles RF PCB layouts through sub-6 GHz comfortably and, with discipline, into the low microwave range. Its impedance-aware stackup editor, differential-pair router, and native 3D model export give you the essential controls a paid tool provides—minus the license fee. The catch is that KiCad has no built-in electromagnetic (EM) solver, so you need an external co-simulation step for anything beyond simple microstrip. This guide walks through the complete KiCad RF design workflow: schematic, stackup, layout, verification, and hand-off to fabrication.

Step 1: RF Schematic Capture in KiCad

Library Strategy

Start by creating a dedicated RF symbol library. Each passive should carry its Q factor, SRF, and package parasitics as symbol fields—these values drive layout decisions later. For connectors (SMA, U.FL, MMCX), use footprints with the manufacturer’s recommended pad geometry; do not scale generic pads.

Power and Signal Domains

Separate power nets (VCC_PA, VCC_LNA) from the start. Assign net classes—50 Ω single-ended, 100 Ω differential, DC power, digital—so that the PCB editor inherits the right width and clearance rules automatically. KiCad’s net-class system propagates from schematic to board, which saves re-entry and prevents mismatches.

Hierarchical Sheets for RF Chains

Place each functional block (LNA, mixer, filter, PA) on its own hierarchical sheet. This keeps the top-level sheet clean and makes it easy to reuse proven blocks across projects—useful if you maintain an SDR board design or similar multi-band platform.

Step 2: Stackup and Material Setup

KiCad’s Board Setup → Physical Stackup editor lets you define layer count, dielectric thickness, copper weight, and—critically—the dielectric constant (Dk) and loss tangent (Df) of each core and prepreg. For RF work below 3 GHz on a budget, standard FR-4 (Dk ≈ 4.3 at 1 GHz, Df ≈ 0.020) is acceptable for short, well-matched traces. Above 3 GHz, or for filters and couplers with tight phase requirements, switch to a high-frequency laminate such as Rogers RO4350B (Dk 3.48 ± 0.05, Df 0.0037 at 10 GHz).

Enter the real Dk at your operating frequency, not the 1 MHz datasheet value. A 10 % Dk error translates directly into a 5 % trace-width error for a 50 Ω microstrip—enough to push return loss from 20 dB to 14 dB at 2.4 GHz.

Recommended Four-Layer RF Stackup

A thinner core between L1 and L2 (e.g., 10 mil / 0.254 mm RO4350B) narrows the 50 Ω microstrip width to roughly 22 mil (0.56 mm), which is easier to route between 0402 pads than the 45+ mil trace you would need on a 30 mil core.

Step 3: RF Layout in KiCad’s PCB Editor

Placement Rules

• Signal flow direction. Place components in the order the signal travels—antenna → filter → LNA → mixer → IF filter → ADC—so traces are short and do not double back.
• Partition the board. Keep digital clocks and switch-mode converters on the opposite side or a separate zone from the RF chain. A physical gap or stitching-via fence between zones cuts coupling by 20–30 dB at 2 GHz.
• Decoupling. Place bypass capacitors (100 pF + 10 nF in parallel) within 1 mm of the supply pin on the same layer, with a via directly to the ground plane—not routed through a trace.

Routing 50 Ω Traces

Use KiCad’s interactive router with the net-class width pre-calculated for your stackup. For a 10 mil RO4350B core, the 50 Ω microstrip width is approximately 22 mil; for 100 Ω edge-coupled differential, the trace/space pair is roughly 12 mil / 8 mil. Verify these numbers with a transmission-line calculator before routing.

Key routing habits:

• Avoid 90° bends; use 45° or curved (arc) routing. KiCad 8 supports arc tracks natively.
• Maintain the ground reference plane unbroken beneath every RF trace. If you must cross a split, stitch both ground regions with vias at the crossing point.
• Match electrical length for differential pairs and balanced structures using KiCad’s length-tuning tool.

Ground Stitching and Via Fencing

Add ground-stitching vias on a grid no wider than λ/20 at your highest frequency of interest. At 5 GHz (λ ≈ 60 mm in free space, ~35 mm in RO4350B), that means vias every 1.7 mm or closer. KiCad’s “Add Via Array” or scripted via-fence plugins handle this efficiently.

Step 4: EM Verification and Co-Simulation

KiCad does not include an EM solver, but its ecosystem connects to several free and commercial options:

The workflow: export the RF-critical copper and dielectric geometry from KiCad as a STEP or DXF, import it into your solver, assign materials and ports, run, and compare S-parameters against your spec. For complex structures, commercial solvers like ADS Momentum or HFSS PCB simulation provide faster convergence and better correlation to measured results. For a broader list of no-cost options, see our roundup of free RF design tools.

KiCad’s Python scripting API also lets you automate geometry export. Community scripts on the KiCad GitLab repository include openEMS export plugins that translate board outlines, copper pours, and via arrays directly into simulation-ready meshes.

Step 5: Design-Rule Checks and Fabrication Output

Custom DRC Rules for RF

KiCad’s custom DRC rule engine (rules file syntax) lets you enforce RF-specific constraints beyond standard clearance checks:

• Minimum trace width per net class (e.g., 50 Ω class ≥ 22 mil).
• Minimum copper-to-edge clearance of 15 mil for controlled-impedance traces near board edges.
• Via-to-trace spacing on RF nets ≥ 3× the dielectric thickness to limit parasitic coupling.

Gerber and Fabrication Notes

Export Gerbers in RS-274X format plus an Excellon drill file. Include a fabrication drawing that calls out the impedance requirement (e.g., “50 Ω ± 10 % microstrip, L1 referenced to L2”) and the target dielectric material and thickness. A complete RF PCB documentation package prevents the fabricator from substituting materials or adjusting trace widths without telling you.

Related Calculators and Tools

Use the tool finder below to locate impedance, stackup, and loss calculators that complement your KiCad RF design workflow. Enter a keyword like “microstrip” or “stackup” to see matching tools instantly.

For example, entering “microstrip impedance” returns a calculator where you plug in your Dk, substrate height, and trace width to confirm the 50 Ω geometry before committing to a layout. If the result shows 48.3 Ω, widen the trace by 1 mil and re-check—this iterative step takes seconds and avoids a board respin.

Common KiCad RF Design Mistakes

• Using the 1 MHz Dk value. FR-4 Dk drops from ~4.7 at 1 MHz to ~4.2 at 2.4 GHz. Using the wrong number shifts your trace width and every impedance-dependent structure.
• Splitting the ground plane under an RF trace. Even a narrow slot forces return current to detour, creating an inductive discontinuity. Route power and digital signals around the RF zone, not through it.
• Ignoring via inductance. A single 10 mil via has roughly 0.5–1 nH of inductance. At 5 GHz that is 15–30 Ω of reactance. Use multiple vias in parallel for component ground pads.
• Skipping EM verification. A schematic simulation with ideal transmission lines will not catch coupling, radiation, or mode conversion. Budget time for at least one EM pass on critical structures.

KiCad RF Design Roadmap and Future Tools

The open-source EDA ecosystem is evolving fast. Below is a roadmap of tools and integrations under development that will further streamline KiCad-based RF workflows—from tighter EM solver coupling to automated impedance-aware autorouting.

Watch this space for updates on native Smith chart integration, improved arc routing for RF stubs, and scripted DRC rules purpose-built for controlled-impedance designs.

Frequently Asked Questions

Is KiCad good enough for RF PCB design?

KiCad is fully capable for RF layouts up to about 6 GHz when you define the stackup correctly, use net-class–driven impedance control, and verify critical structures with an external EM solver such as openEMS or a commercial tool. Beyond 6 GHz, tighter manufacturing tolerances and the lack of a built-in field solver make commercial EDA suites more practical.

How do I set 50 Ω trace width in KiCad?

Calculate the required width using a microstrip impedance formula or calculator for your specific Dk and dielectric height. Enter that width as the default for a “50ohm” net class in Board Setup → Net Classes. The interactive router then applies it automatically to every net in that class.

Can KiCad simulate S-parameters?

Not natively. KiCad includes a basic SPICE simulator (ngspice) for time-domain and AC analysis, but S-parameter and full-wave EM simulation require an external tool. openEMS (free FDTD) and Qucs-S (free circuit/S-param) are the most common open-source companions.

What file format should I export for EM simulation?

STEP is preferred for 3D solvers (HFSS, CST). For 2D planar solvers (Momentum, Sonnet), export individual copper layers as DXF or use a KiCad-to-solver Python script. Always include the board outline and drill file so the solver geometry matches the real board.