RF PCB Documentation Package: What to Send the Fab

Why RF PCB Documentation Demands More Than Standard Boards

An RF PCB documentation package is the complete set of fabrication files, material callouts, impedance specifications, and inspection criteria you deliver to the fab so your high-frequency board is built to spec on the first run. Unlike a digital-only board where a Gerber set and a drill file may suffice, an RF printed circuit board carries tight dielectric-constant tolerances, controlled-impedance traces, and loss budgets that must be communicated explicitly—because the fab cannot infer them from copper artwork alone.

Missing or ambiguous documentation is the single largest cause of RF prototype respins. A forgotten Dk callout can shift a 50 Ω microstrip by 3–5 Ω; an unlabeled via fence can be omitted during CAM review; an unspecified surface finish can add 0.02 dB/cm of insertion loss at millimeter-wave frequencies. Every item below exists to prevent a specific, real failure mode.

Core Files Every RF Fab Expects

Gerber / ODB++ / IPC-2581 Artwork

Export every copper layer, solder mask, silkscreen, paste stencil, and board outline as individual Gerber RS-274X files, or use a single ODB++ or IPC-2581 package that bundles artwork with netlist and stackup data. For RF boards, confirm that your CAD tool exports fine-arc interpolation (G02/G03) rather than chord approximation on curved traces such as Wilkinson divider arcs or radial stubs, because chord segmentation can introduce impedance ripple.

Drill Files and Slot Data

Provide Excellon drill files for plated through-holes, non-plated holes, blind vias, buried vias, and back-drilled stubs separately. Back-drill depth and tolerance (typically ±4 mil / ±0.1 mm) must appear in the fab drawing, not buried in a readme. If your design uses laser-drilled microvias for RFIC escape routing, call out the target diameter (often 4 mil / 0.1 mm) and aspect ratio limit (usually ≤ 1:1 for HDI).

Netlist (IPC-D-356A)

An IPC-D-356A netlist lets the fab run electrical test (flying probe or fixture) against your design intent. For RF boards, this file also helps the fab verify that ground-stitching vias and shielding fences are connected to the correct net—catching opens that would destroy isolation between channels.

The Fab Drawing: Where RF Details Live

The fabrication drawing is the single most important document in your RF PCB documentation package. It is the legally binding specification. Everything the fab cannot extract from Gerbers must be stated here. A thorough RF design documentation checklist will keep you from omitting critical items.

Material and Stackup Callout

Name the exact laminate grade—not just “Rogers” but “Rogers RO4350B, Dk 3.48 ± 0.05 at 10 GHz per IPC-TM-650 2.5.5.5, 0.010 in (0.254 mm) core.” If your design mixes materials (e.g., RO4350B signal layers bonded with FR-4 structural layers using Rogers RO4450F prepreg), draw a cross-section showing every layer, its material, nominal thickness, and copper weight. For designs operating above 24 GHz, specifying Dk at the actual operating frequency matters because Dk can shift 1–3 % between 10 GHz and 77 GHz depending on the resin system. When evaluating high-frequency laminates, a side-by-side RF laminate comparison helps narrow the field before you lock the callout.

Controlled-Impedance Table

List every impedance class in a table on the fab drawing. Include the target impedance, tolerance, reference layer(s), trace width, and the layer pair. A typical table looks like this:

The fab’s CAM engineer will re-simulate these in a 2-D field solver and may adjust trace width by 0.2–0.5 mil to hit the target after accounting for etch compensation. If your design cannot tolerate any width adjustment (e.g., a coupled-line filter), state “no width modification permitted—adjust dielectric thickness instead” explicitly.

Surface Finish

Surface finish affects both solderability and RF loss. ENIG (electroless nickel / immersion gold) is common but adds a 100–200 µin nickel barrier that increases skin-effect loss above 10 GHz. For millimeter-wave work, immersion silver or hard electrolytic gold over a copper base gives lower loss. State the finish, its thickness range, and any keep-out zones (e.g., “no ENIG on microstrip traces in area A; use bare copper with OSP”).

Solder Mask and Coverlay Notes

Solder mask adds a dielectric layer (Dk ≈ 3.5–4.2) on top of microstrip traces, which shifts impedance downward. Many RF designs specify solder-mask openings over all controlled-impedance traces. If you need mask for handling or assembly reasons, call out the mask thickness and include it in your impedance model. Understanding how dielectric constant affects trace impedance makes this trade-off clearer.

Back-Drill and Via Specifications

For designs above about 5 GHz, via stubs act as resonant antennas that create notches in the insertion-loss curve. Back-drilling removes the unused stub portion. Document the target stub length after back-drill (commonly ≤ 10 mil / 0.25 mm), the drill diameter (typically 2–4 mil larger than the via barrel), and which vias require back-drilling (call them out on a dedicated back-drill layer or with a table of coordinates).

Supporting Documents That Prevent Misbuilds

Bill of Materials for Laminates and Prepregs

A laminate BOM lists every core and prepreg sheet by manufacturer part number, thickness, Dk/Df at the relevant frequency, copper foil type (standard ED, RTF, VLP), and approved alternates if any. This is especially important for hybrid stackups where the fab may stock a similar-sounding grade that differs in Df by 0.002—enough to blow a loss budget on a 77 GHz radar front end.

Assembly Drawing vs. Fab Drawing

Keep them separate. The fab drawing governs bare-board fabrication; the assembly drawing governs component placement, reflow profile, and conformal coating. Combining them creates ambiguity about who owns which tolerance. Your complete documentation package should contain both as distinct files.

Test Coupon and TDR Requirements

If your impedance tolerance is ±5 % or tighter, specify impedance test coupons on the panel border. Reference IPC-6012 Class 3 or 3A for coupon design rules and acceptance criteria. For differential pairs, request both odd-mode and even-mode coupon structures. Ask the fab to report TDR traces (not just pass/fail) so you can see impedance uniformity along the coupon length.

First Article Inspection (FAI) Documentation

A first article inspection verifies that the initial production unit matches every dimension, material, and electrical parameter in your documentation package. For aerospace and defense RF boards, FAI is typically governed by AS9102 and may also need to satisfy AS9100 quality system requirements. Even for commercial RF work, requesting an FAI report catches systemic errors before a full lot is built.

An FAI package usually includes: dimensional inspection data (layer-to-layer registration, hole placement, board outline), cross-section microphotographs (plating thickness, dielectric thickness), impedance coupon TDR results, ionic contamination or SIR test results, and a material traceability certificate linking each laminate lot to the vendor’s CoC.

Use the assistant below to generate a structured FAI documentation checklist tailored to your board’s complexity and industry requirements. Enter your layer count, material type, and target standard, and it returns the inspection items and acceptance criteria you should request from the fab.

For example, a 6-layer hybrid stackup on RO4350B / FR-4 targeting IPC-6012 Class 3 will produce an FAI checklist that includes dielectric-thickness verification on every RO4350B core (nominal 10.0 mil, acceptance ±0.5 mil), copper plating thickness in through-holes (minimum 1.0 mil per IPC-6012 Class 3), and impedance coupon results for each controlled-impedance class with a ±5 % window. Review this checklist with your fab before they start tooling—agreeing on acceptance criteria up front eliminates disputes at delivery.

Common Documentation Mistakes and How to Fix Them

• Dk specified at 1 MHz instead of operating frequency. Many datasheets list Dk at 1 MHz for comparison purposes, but RF designs need the value at 1 GHz, 10 GHz, or higher. Always state the test frequency next to the Dk value.
• Missing copper-foil type. Standard electrodeposited (ED) foil has higher surface roughness than reverse-treated (RTF) or very-low-profile (VLP) foil. At 28 GHz, switching from standard ED to VLP can reduce conductor loss by 15–25 %. If your loss budget depends on smooth foil, call it out.
• Gerbers without an origin datum. When the fab panelizes your board, a missing or ambiguous origin causes layer-to-layer misregistration. Place a single, clearly marked datum point at the same coordinate in every Gerber layer.
• No version control. Stamp every file with a revision letter and date. The fab drawing should carry a revision block with ECO numbers. Without this, the fab may build from a superseded file set sitting in an old email thread.
• “Per fab’s standard process” used as a specification. This transfers design responsibility to the fab. Every parameter that affects RF performance—etch factor, plating chemistry, lamination pressure profile—should either be specified or explicitly delegated with a tolerance window.

File Naming and Delivery Format

A clean file package reduces CAM review time and NRE charges. Use a flat naming convention: ProjectName_RevA_LayerFunction.gbr (e.g., RadarRx_RevC_Top_Cu.gbr). Include a readme that maps every filename to its layer and function. Deliver the package as a single ZIP archive; do not split files across multiple emails. For a detailed rundown of exactly which files to send your PCB fab, see our companion guide.

Consider using Altium’s Output Job files or KiCad’s plot manager to automate Gerber and drill generation, ensuring the same settings every release. Automation eliminates the class of errors where an engineer accidentally exports with the wrong units (imperial vs. metric drill files are a perennial source of 2.54× scaling disasters).

Revision Control and Change Management

RF boards often go through multiple impedance-tuning iterations before production release. Maintain a revision history table in the fab drawing that logs every change: what was modified, why, and which layers are affected. When issuing a revision, re-export the entire file set—never send a partial update with instructions like “replace only the top copper layer.” Partial updates are the fastest path to a misbuilt board.

For programs under aerospace quality systems, change management may require formal deviation approval before the fab can proceed. Build that lead time into your schedule.

Quick-Reference Documentation Checklist

Frequently Asked Questions

What file format is best for RF PCB documentation?

ODB++ or IPC-2581 packages are preferred because they embed the netlist, stackup, and artwork in one intelligent file, reducing the chance of mismatched data. If your fab only accepts Gerbers, supplement them with a detailed fab drawing and an IPC-D-356A netlist.

Should I include simulation data in my fab package?

Include the impedance targets and the Dk/Df values you used in simulation, but not the simulation project files themselves. The fab re-simulates with their own process parameters (etch factor, plating build-up) to determine the as-manufactured trace width. Providing your assumptions lets them flag discrepancies early.

How do I specify material substitutions?

List approved alternates in the laminate BOM with their Dk/Df values and note the maximum allowable Dk deviation (e.g., “alternate must have Dk within ±0.05 of primary at 10 GHz”). If no substitute is acceptable, write “no substitution permitted” on the fab drawing. Check the vendor’s published laminate datasheets to confirm the parameters you’re specifying.

Do I need a separate back-drill drawing?

Yes, if your design has more than one back-drill depth or selective back-drilling. Provide a dedicated Gerber layer (or coordinate table) showing which vias are back-drilled, from which side, and to what target depth. A single global note like “back-drill all vias” is insufficient when some vias transition between different layer pairs.

When is an FAI report worth requesting?

Always request FAI on the first lot of a new design, after any revision that changes the stackup or impedance classes, and whenever you change fabricators. The cost is typically a few hundred dollars and one to two extra business days—trivial compared to the cost of scrapping a production lot.