Test Coupon Design for RF & Microwave PCBs

What Is RF Test Coupon Design and Why Does It Matter?

Test coupon design is the practice of creating small, dedicated verification structures on the same fabrication panel as production RF boards, ensuring that the laminate, etching, plating, and stackup meet electrical and mechanical specifications. For RF and microwave work, test coupon design goes beyond simple continuity: it validates controlled impedance, dielectric loss, copper roughness effects, and long-term reliability under environmental stress. Without well-designed coupons, you are trusting the fabricator’s process without board-level evidence—a risk that grows with frequency.

The structures described below cover the five coupon families most relevant to high-frequency boards: impedance verification, insertion-loss characterization, surface insulation resistance (SIR), peel strength, and thermal reliability. Each section explains the geometry, placement rules, and what the measurement actually tells you about your test coupon design choices.

Impedance Verification in Test Coupon Design

Structure Types

Impedance coupons replicate the trace geometry of controlled-impedance nets on the production board. The most common structures are:

• Single-ended microstrip – a surface trace over a ground plane, typically 50 Ω.
• Single-ended stripline – an inner-layer trace between two reference planes, also typically 50 Ω.
• Differential microstrip and stripline – paired traces for 85 Ω, 90 Ω, or 100 Ω differential impedance.
• Coplanar waveguide (CPW / GCPW) – surface trace with coplanar ground, common at millimeter-wave frequencies.

Each structure must match the production trace width, spacing, copper weight, dielectric thickness, and layer assignment exactly. A coupon on layer 3–4 does not validate a layer 1–2 microstrip. Impedance coupon versus real-trace correlation depends on how faithfully the coupon mirrors the production geometry.

Sizing and Probe Launch

Time-domain reflectometry (TDR) is the standard measurement method per IPC-TM-650, method 2.5.5.7. The coupon trace must be long enough for the TDR pulse to reach a stable impedance plateau before the far-end reflection returns. A minimum electrical length of 150 ps one-way (roughly 25 mm / 1 in on FR-4, shorter on low-Dk laminates) is a safe starting point; many fabricators use 150 mm (6 in) lines for comfort. Probe pads at each end should match the pitch of the TDR probe—typically 1.00 mm or 1.27 mm center-to-center for GS or GSG configurations.

Tolerance is specified per IPC-2141A and IPC-6012 Class 3: ±10 % for single-ended, ±10 % for differential, tightened to ±5 % by negotiation for RF work above 10 GHz. Whether every lot needs a TDR report depends on your risk posture—deciding when impedance testing is necessary is a cost-versus-risk conversation worth having early.

Insertion-Loss (S-Parameter) Coupons

Why Impedance Alone Is Not Enough Above 5 GHz

TDR tells you the characteristic impedance but says almost nothing about dielectric loss (Df), copper roughness loss, or radiation loss—all of which dominate performance above a few gigahertz. An insertion-loss coupon is a transmission-line segment measured with a vector network analyzer (VNA) to extract S21 per unit length, typically reported in dB/inch or dB/cm at specific frequencies. Including this coupon type in your test coupon design is critical for any board operating above 5 GHz.

Coupon Geometry

A practical insertion-loss coupon set includes two traces of different lengths on the same layer—for example, 50 mm and 150 mm. Subtracting the S21 of the short line from the long line removes the launch discontinuity and connector effects, giving a clean per-unit-length loss figure. This differential-length method is described in the IEEE 370 de-embedding framework.

Key design rules:

• Use the same trace width, stackup layer, and ground-plane spacing as the production net you care about most.
• Terminate both ends in GSSG or GSG pads compatible with your probe or SMA connector footprint.
• Keep the coupon trace straight—bends add radiation and mode-conversion artifacts.
• Place ground vias along the coupon edge at ≤ λ/20 spacing at the highest test frequency to suppress parallel-plate modes.

For boards built on high-frequency laminates such as RO4350B (Dk 3.48, Df 0.0037 at 10 GHz) or RO3003 (Dk 3.00, Df 0.0013), the insertion-loss coupon is often the single most valuable quality gate, because Df variation between laminate lots directly shifts filter passband loss and receiver noise figure.

Surface Insulation Resistance (SIR) Coupons

What SIR Measures

SIR testing applies a DC bias (typically 50 V or 100 V) across an interdigitated comb pattern under elevated temperature and humidity (e.g., 85 °C / 85 % RH per IPC-TM-650 method 2.6.3.7) and monitors leakage current over 168 hours or longer. The result, expressed in ohms, indicates whether ionic contamination, flux residue, or moisture absorption degrades the surface dielectric. A passing threshold is usually ≥ 10⁸ Ω; high-reliability RF assemblies often demand ≥ 10⁹ Ω.

Use the tool below to determine whether your product class and operating environment require SIR testing on this build.

If the tool indicates SIR testing is warranted, place the comb pattern on the same surface layer and solder-mask opening style as the densest RF area of your production board. The comb pitch should match or be tighter than the minimum conductor spacing on the production design—commonly 0.15 mm (6 mil) line-and-space for high-density RF boards. An ionic cleanliness screen (ROSE or ion chromatography) is a faster incoming check, but SIR remains the definitive long-term surface-quality test.

Peel Strength and Bond Quality Coupons

On PTFE-based laminates (RT/duroid 5880, TLY-5, DiClad 880), copper adhesion is inherently lower than on FR-4 because PTFE is chemically inert. A peel-strength coupon—a 1 oz copper strip typically 3.18 mm (0.125 in) wide—is pulled at 90° or 180° to measure bond force in N/mm (or lb/in). IPC-TM-650 method 2.4.8 defines the procedure. Peel strength testing on PTFE substrates is essential whenever you use a filled or unfilled PTFE laminate, because process variations in plasma treatment or sodium-etch surface preparation can halve the bond strength without any visible defect.

Place the peel coupon on the panel border, oriented so the pull direction is along the machine direction of the laminate. Minimum acceptable peel strength for electrodeposited copper on PTFE is typically 0.70 N/mm (4 lb/in); design-for-reliability targets should be ≥ 1.05 N/mm (6 lb/in).

Thermal and Mechanical Reliability Coupons

Thermal Shock and Cycling

Plated through-holes and microvias on RF boards face the same thermal-expansion stress as digital boards—often worse, because mixed-dielectric stackups (e.g., RO4350B cores with FR-4 prepreg) create CTE mismatches. A daisy-chain coupon connecting a series of vias across all layers lets you monitor resistance shift during thermal shock testing (–55 °C to +125 °C air-to-air, or –65 °C to +150 °C for mil-spec) and IST and CAF reliability testing.

Design the daisy chain with at least 30 via transitions per net to accumulate enough resistance change for a sensitive four-wire measurement. Include both PTH (≥ 0.3 mm drill) and microvia (≤ 0.15 mm drill) chains if both exist in the production design.

Vibration Resilience

RF boards in aerospace, automotive radar (77 GHz FMCW modules), and defense systems endure sustained vibration. While vibration testing is performed on the assembled board rather than a bare coupon, selecting the right vibration profile early influences your overall test coupon design and test-vehicle planning. Use the tool below to match your application environment to an appropriate vibration test standard.

If the selector points to MIL-STD-810 or RTCA DO-160, plan a dedicated test vehicle—a small populated board with representative BGA, QFN, and RF connector joints—fabricated from the same panel as the production run. This vehicle rides alongside the production boards through assembly and then goes to the shaker table, giving you solder-joint and via-reliability data specific to your stackup and finish.

Coupon Placement and Panel Layout Rules

Where you put coupons on the panel matters as much as what they contain. Good test coupon design accounts for fabrication variation across the panel area. Practical rules:

• Place impedance coupons on at least two edges of the panel (top and bottom, or left and right) to capture etching and plating variation across the panel. IPC-6012 Class 3 requires at least one coupon per impedance class per panel.
• Orient coupons parallel to the direction of panel travel through the etcher, so the coupon trace experiences the same etch chemistry exposure as the production traces.
• Keep coupons inside the panel border rail, at least 10 mm from the routed edge, to avoid edge effects in plating thickness.
• Never share a coupon across different stackup configurations on a multi-design panel. Each unique stackup needs its own coupon set.
• Label each coupon with layer pair, target impedance, and a unique serial so TDR reports trace back to a specific panel.

If panel real estate is tight, work with your fabricator to place coupons in the breakaway rail or in a dedicated coupon strip that ships with the boards. Removing coupons from the panel to save space removes your only objective quality evidence—an unwise trade-off on any RF build.

Test Coupon Design Checklist

1. List every controlled-impedance net class (single-ended and differential) and assign a coupon structure to each.
2. Add an insertion-loss coupon pair (short + long) for the highest-frequency signal layer.
3. Include an SIR comb if the board will be assembled with no-clean flux or will operate in a humid environment.
4. Include a peel-strength strip if any layer uses PTFE or ceramic-filled hydrocarbon laminate.
5. Add a daisy-chain via coupon for any board with ≥ 8 layers, blind/buried vias, or mixed-dielectric stackup.
6. Verify probe-pad pitch matches your TDR and VNA probe or connector.
7. Place coupons on two panel edges minimum; label with layer, impedance, and serial.
8. Specify acceptance criteria (impedance tolerance, max insertion loss, min SIR, min peel force) on the fabrication drawing.

Getting test coupon design right at the layout stage prevents arguments at incoming inspection. If you need help mapping coupon structures to a specific stackup, a stackup consultation can model impedance and loss before you commit artwork.

FAQ

How many impedance coupons per panel do I need?

IPC-6012 Class 3 requires at least one coupon per controlled-impedance class per panel. For RF boards, best practice is two coupons per impedance class—one near each panel edge—to capture cross-panel etch variation.

Can I use the same coupon for TDR and VNA measurement?

Yes, if the coupon has proper GSG launch pads and is long enough (≥ 50 mm for VNA de-embedding). However, a dedicated differential-length pair gives cleaner VNA loss data because it cancels launch effects.

Do I need insertion-loss coupons on FR-4 boards?

Below about 3 GHz, FR-4 insertion loss is usually predictable enough that impedance coupons alone suffice. Above 5 GHz—or whenever Df matters to your link budget—add loss coupons. On low-loss laminates like RO4350B or Megtron 6, loss coupons are standard practice at any frequency above 1 GHz because the laminate is chosen specifically for its Df, and you need to verify it.

Where should SIR coupons be placed on the panel?

Place SIR comb patterns on the same surface layer and solder-mask style as the densest signal area of the production board. They belong inside the panel array, not on the breakaway rail, because solder-mask registration and thickness vary with position.

What is the minimum trace length for a TDR impedance coupon?

The trace must be long enough for the TDR system’s rise time to resolve a stable impedance plateau—typically a minimum of 25 mm (1 in) on FR-4 or 20 mm on low-Dk laminates. Most fabricators standardize on 150 mm (6 in) to provide margin and accommodate slower instruments.