HFSS PCB Workflow | Import, Setup, Solve, Correlate

What Is an HFSS PCB Workflow?

HFSS (High-Frequency Structure Simulator) is Ansys’s 3-D full-wave finite-element electromagnetic solver. An HFSS PCB workflow is the end-to-end process of importing a board layout, assigning accurate materials and ports, running an adaptive frequency sweep, and correlating the results against network-analyzer measurements. When done correctly, this workflow closes the gap between schematic-level models and physical reality, routinely achieving ±0.5 dB insertion-loss agreement through 40 GHz and beyond. Understanding each step—and the places where small errors compound—is the difference between a clean first spin and a costly respin. If you are new to the distinction between RF boards and conventional digital boards, our overview of what constitutes an RF PCB provides useful context.

Step 1: Geometry Import

Supported Formats

HFSS accepts board geometry through several paths. The most common are ODB++ archives exported from Cadence Allegro or Altium Designer, and EDB files from Ansys’s own Electronics Desktop. A third option is direct 3-D model import via STEP or SAT when only a sub-section (a connector footprint, a filter, an antenna element) needs full-wave treatment.

What to Keep, What to Remove

Importing the entire board is tempting but usually unnecessary and computationally expensive. Identify the region of interest—a transmission-line transition, a coupled-filter section, a patch-antenna feed—and clip the geometry to that area plus at least five substrate thicknesses of margin on each side. Remove power-plane copper islands, mounting holes, and silkscreen that have no electromagnetic effect. Keep every ground via within the clipped region; deleting even a few can shift a resonance by hundreds of megahertz at millimeter-wave frequencies.

Geometry Healing

After import, run HFSS’s geometry-validation tool. Look for overlapping polygons on the same layer, zero-thickness slivers, and unmerged vertices. These artifacts cause meshing failures or, worse, invisible mesh distortion that makes the solution converge to a wrong answer. Spending 15–20 minutes on geometry healing saves hours of troubleshooting later.

Step 2: Stackup and Material Assignment

Material accuracy dominates simulation accuracy. Assign each dielectric layer its frequency-dependent Dk and Df from the laminate vendor’s datasheet—not the “typical” value printed on a distributor page. For example, Rogers RO3003G2 specifies a Dk of 3.00 ± 0.04 at 10 GHz using the clamped-stripline method, and its Df is 0.0010 at the same frequency. Entering a generic “3.0” without the loss tangent’s frequency dependence will under-predict insertion loss above 20 GHz.

Conductor Modeling

For traces below roughly 6 GHz, a simple finite-conductivity boundary with σ = 5.8 × 10⁷ S/m for copper is adequate. Above that, surface roughness increasingly matters. HFSS offers the Groiss, Huray, and Hammerstad-Jensen roughness models. The Huray model, which approximates the copper surface as a field of hemispherical nodules, correlates best with electrodeposited copper profiles (RMS roughness 0.3–1.5 µm typical on standard HF laminates). Enter the nodule radius and hall-sphere density from the copper-foil vendor’s data; guessing these parameters can introduce 0.3–0.5 dB/inch error at 28 GHz.

Understanding how Dk is measured and specified helps you choose the right datasheet value for your simulation frequency.

Solder-Mask and Plating

Solder mask has a Dk around 3.3–4.0 and a Df of 0.015–0.025, depending on the formulation. On exposed microstrip above 10 GHz, ignoring the mask shifts effective Dk enough to detune a quarter-wave stub by several percent. Model it as a conformal dielectric layer with its actual thickness (typically 15–25 µm over copper). ENIG finish adds a 3–5 µm nickel barrier whose ferromagnetic loss is significant above 20 GHz; model it as a separate thin layer or accept a known offset in correlation.

Step 3: Port Setup and Excitation

Wave Ports vs. Lumped Ports

Wave ports are the gold standard when the cross-section is well-defined—microstrip, stripline, coplanar waveguide. They compute the exact modal field pattern and de-embed the reference plane to the trace edge. Use a wave-port height of 8–10× the substrate thickness and a width of 5–8× the trace width to avoid port-boundary truncation artifacts.

Lumped ports suit component pads (SMD resistors, capacitors, connectors) where the current path is short and the field is quasi-static. A lumped port placed across a 0402 pad pair with a 50 Ω normalization impedance gives reliable results up to about 20 GHz; beyond that, the port’s parasitic inductance starts to matter and a wave-port or a full connector model is preferable.

De-Embedding

Always de-embed feed lines back to a consistent reference plane. If you are comparing S-parameters against a VNA measurement that uses TRL calibration at the board edge, set the HFSS de-embed length to match. A 1 mm de-embed mismatch on a 50 Ω microstrip at 28 GHz introduces roughly 30° of phase error—enough to invalidate a filter or coupler design.

Step 4: Meshing Strategy

HFSS uses adaptive tetrahedral meshing: it solves, identifies high-error regions, refines, and re-solves until ΔS (the maximum change in S-parameters between passes) drops below a threshold. The default ΔS target is 0.02; for PCB work through 40 GHz, tightening it to 0.01 with a minimum of three converged passes is a practical starting point.

Mesh Operations That Matter

• Length-based mesh on traces: Set a maximum element length of λ/8 at the highest solve frequency on all signal conductors. At 28 GHz on RO4350B (Dk 3.48), λ_eff ≈ 5.7 mm, so the element length should be ≤ 0.7 mm.
• Skin-depth layers: Enable automatic thin-layer meshing on conductors so the solver captures current crowding without manual layering.
• Via meshing: Cylindrical vias in a via fence need at least 6–8 elements around their circumference; fewer elements create artificial resonance artifacts.

A well-meshed single-transition model (connector-to-microstrip, for example) typically finishes in 20–60 minutes on a workstation with 64 GB RAM and 8–12 CPU cores. Whole-board models can run into hundreds of gigabytes; this is why clipping geometry in Step 1 matters so much.

Step 5: Frequency Sweep and Solver Settings

HFSS offers three sweep types:

For a typical PCB interconnect from 0.1 to 40 GHz, the fast sweep with 401 points gives a smooth S₂₁ and S₁₁ curve in one-tenth the time of a discrete sweep. Switch to discrete or broadband adaptive when the structure has high-Q resonances (cavity filters, SIW structures) where interpolation can miss a notch.

Set the solution frequency to the highest frequency of interest. HFSS meshes at this frequency and assumes the mesh is adequate for all lower frequencies—which is generally true for PCB structures that do not have electrically large cavities at mid-band.

Step 6: Post-Processing and Sanity Checks

S-Parameter Inspection

Before comparing to measurements, verify internal consistency:

• Passivity: |S₁₁|² + |S₂₁|² ≤ 1 at every frequency. If the sum exceeds 1 by more than 0.01, the mesh has not converged.
• Reciprocity: For passive structures, S₁₂ should equal S₂₁ within 0.01 dB. A discrepancy indicates asymmetric meshing or port issues.
• Low-frequency limit: A 50 Ω through-line should show S₁₁ below −30 dB at 100 MHz. If it does not, check port impedance normalization.

Field Visualization

Plot the E-field magnitude on the trace cross-section at the highest frequency. You should see a clean quasi-TEM pattern for microstrip, or a symmetric field for stripline. Unexpected hot spots near via barrels or plane edges reveal coupling paths that the schematic model missed—information that is gold for debug. Our RF prototype debug workflow describes how to translate these simulation clues into bench-level fixes.

Step 7: Correlation to Measurements

Correlation is where the HFSS PCB workflow pays off—or exposes its weaknesses. The goal is to overlay simulated and measured S-parameters and achieve agreement within defined tolerances.

Calibration Alignment

Match the measurement calibration method to the simulation reference planes. If you use SOLT calibration at the coax connector interface, include a full 3-D connector model in HFSS. If you use on-board TRL calibration structures, de-embed the simulation to the same thru-line midpoint. Mismatched reference planes are the single most common cause of poor correlation.

Typical Correlation Targets

When correlation falls outside “acceptable,” work through the error sources in order of typical impact: Dk tolerance → copper roughness → solder-mask dielectric → etch compensation → connector model fidelity. Adjusting Dk by ±2 % and re-solving often closes the gap for insertion loss; adjusting roughness parameters closes it for the loss slope versus frequency.

Feeding Results Back to Layout

Once correlated, export the S-parameter Touchstone file (.s2p or .snp) and drop it into your circuit simulator as a verified black-box model. This is far more reliable than the lumped-element equivalent circuits that ship with connector datasheets. For complex boards, the correlated HFSS model also feeds the RF documentation package you send to your fabricator, giving them the impedance and loss targets your design depends on.

HFSS vs. Other Full-Wave Solvers for PCB Work

HFSS is not the only option. Comparing it to a time-domain solver such as CST Studio Suite helps clarify when each tool earns its license cost:

Many teams use both: HFSS for the critical narrowband structures and a time-domain solver for broadband interconnect sweeps. The differences between high-frequency and high-speed design disciplines often dictate which solver gets the first pass.

Common Pitfalls and How to Avoid Them

• Using nominal Dk instead of design Dk: Laminate vendors publish a “design Dk” that accounts for the resin-to-glass ratio in your actual stackup. The Rogers Microwave Tools suite generates design-Dk values for specific constructions—use them.
• Ignoring etch compensation: A 5 mil (0.127 mm) trace drawn in the EDA tool may etch to 4.5 mil (0.114 mm) on the finished board. Model the as-fabricated width, not the artwork width, for correlation.
• Under-meshing ground vias: Stitching vias that appear electrically short at 5 GHz become quarter-wave stubs at 30 GHz. Mesh them properly or accept that your model diverges above the via’s first resonance.
• Forgetting solder joints: A BGA or QFN solder joint adds 30–80 pH of inductance per pad. For components operating above 10 GHz, model the solder bump geometry explicitly.

Achieving First-Pass Success

The payoff of a disciplined HFSS PCB workflow is a board that works on the first build. Every hour invested in accurate material entry, mesh convergence, and reference-plane alignment reduces the probability of a respin. For a structured approach to making that happen across the entire design-to-fabrication chain, see our guide to achieving first-pass success in RF PCB.

FAQ

Can HFSS simulate an entire RF PCB?

Technically yes, but practically it is rarely efficient. A full board at 28 GHz can require 200+ GB of RAM. The standard approach is to segment the board into critical sub-structures (transitions, filters, antenna elements), simulate each in HFSS, and reconnect them as S-parameter blocks in a circuit simulator.

What mesh convergence target should I use for PCB work?

A ΔS of 0.01 with a minimum of three converged passes is a reliable starting point. Tighter targets (0.005) are warranted for narrowband filters with loaded Q above 50 but rarely change broadband interconnect results enough to justify the added solve time.

How do I get accurate Dk values for my HFSS model?

Use the laminate vendor’s datasheet value at the frequency closest to your operating band, measured by the clamped-stripline or split-post-dielectric-resonator method. For Isola Astra MT77, for instance, the datasheet specifies Dk = 3.00 at 10 GHz by clamped stripline. Avoid values from the IPC-TM-650 2.5.5.5 method at 1 MHz—they are not representative of microwave behavior.

Do I need HFSS for designs below 3 GHz?

Below about 3 GHz, 2.5-D planar solvers (Momentum, Sonnet) and well-characterized transmission-line models usually suffice. HFSS becomes essential when 3-D effects dominate: vertical transitions, cavity modes, thick substrates relative to wavelength, or structures with significant radiation. Consult the Ansys HFSS product page for current solver capabilities and licensing options.

How long does a typical HFSS PCB simulation take?

A single microstrip-to-stripline transition model (roughly 15 mm × 10 mm × 1.5 mm) solved from 0.1 to 40 GHz with a fast sweep typically completes in 20–45 minutes on a modern 16-core workstation with 64 GB RAM. Larger structures—a 4 × 4 patch array, for example—can take 4–8 hours and require 128 GB or more.