RF PCB Design Checklist | 60-Point Pre-Tapeout

Why You Need a Formal RF PCB Design Checklist

A single missed via stitching row or an uncontrolled return-path transition can shift insertion loss by 1–2 dB and push a filter’s passband edge outside spec—problems that are invisible until you measure the first prototype. A written, 60-point RF PCB design checklist catches these errors at the desk, where fixing them costs minutes instead of weeks. The checklist below is organized in the order you should execute it: schematic integrity first, then stackup, transmission lines, grounding, components, EMC, DFM, documentation, and final tapeout sign-off.

Section 1 — Schematic and Netlist Integrity (Points 1–8)

1. Schematic ERC clean. Zero unconnected pins, zero duplicate net names. Run ERC after every edit, not just at the end.
2. RF signal path annotated. Mark each net that carries RF with its target impedance (50 Ω, 100 Ω diff, etc.) and frequency band.
3. Power rail decoupling complete. Every VCC pin has a local bypass cap placed in schematic; value chosen per IC datasheet (typically 100 pF + 10 nF for RF ICs up to 6 GHz).
4. DC bias networks verified. Bias tee inductors and blocking caps have SRF above the operating frequency. Confirm with RF inductor and capacitor SRF selection guidelines.
5. Gain and NF budget matches simulation. Cascade analysis accounts for connector, PCB trace, and filter losses—not just active-device data-sheet values.
6. S-parameter models assigned. Every passive two-port and four-port has a vendor-supplied Touchstone file or a measured model, not an ideal element.
7. Test points and debug access. At least one 50 Ω probe point per RF stage; pads sized for a ground-signal-ground probe tip (typically 150 µm pitch at mmWave, 500 µm at sub-6 GHz).
8. Net class constraints exported. Impedance targets, spacing rules, and differential pair assignments are written into the constraint file before placement starts.

Section 2 — Stackup and Material (Points 9–18)

9. Laminate grade selected for frequency. FR-4 (Dk ≈ 4.3, Df ≈ 0.020) is marginal above 3 GHz. For 5–40 GHz, specify a low-loss laminate such as Rogers RO4350B (Dk 3.48, Df 0.0037) or RO3003G2 (Dk 3.00, Df 0.0010).
10. Dk tolerance budgeted. A ±0.05 Dk variation shifts a 50 Ω microstrip width by roughly 0.5 mil (0.013 mm) on a 10-mil (0.254 mm) core—confirm your trace width can absorb this.
11. Prepreg and core thicknesses confirmed with fab. Never assume catalog values; request the fabricator’s actual pressed-thickness data for your specific resin content.
12. Copper weights consistent. Mixing ½ oz (17 µm) and 1 oz (35 µm) copper on the same layer changes etch compensation and impedance; flag it in the stackup drawing.
13. Reference planes continuous under every RF trace. No splits, no slots, no relief cuts under signal lines. A 10-mil gap in the ground plane under a 50 Ω microstrip at 5 GHz can cause a 3–5 dB return-loss dip.
14. Layer assignment logical. RF signal layers adjacent to unbroken ground planes; digital I/O on inner layers sandwiched between power and ground.
15. Hybrid stackup registration. If mixing PTFE and FR-4, confirm the fab can bond them (typically requires a thermoplastic bonding film like Rogers CuClad or FEP) and that the z-axis CTE mismatch is within IPC-6012 Class 3 limits.
16. Finished board thickness and tolerance noted. Critical for connectors with controlled-depth press-fit pins; typical tolerance is ±10 % of nominal.
17. Surface finish compatible with RF. ENIG (3–5 µin Au over 150 µin Ni) is standard; for frequencies above 30 GHz, consider ENEPIG or immersion silver to reduce nickel skin-effect loss.
18. Stackup drawing signed off by fab. The RF documentation package must include a cross-section with all dielectric constants, thicknesses, and copper weights.

Section 3 — Transmission Lines and Impedance (Points 19–28)

19. Impedance calculated, not guessed. Use a field solver (not the IPC-2141 approximation) for every controlled-impedance net. Enter the fab-confirmed Dk, copper thickness, and etch factor.
20. Microstrip vs. stripline decision documented. Microstrip is easier to probe and tune; stripline offers better isolation and less radiation. Record why you chose each.
21. Coplanar waveguide (CPWG) gap dimensioned. The gap-to-trace ratio sets mode balance; keep the gap ≤ 2 × substrate height to suppress the parallel-plate mode.
22. Differential pairs length-matched. Intra-pair skew < 1 % of the bit period or < 2° of phase at the carrier frequency, whichever is tighter.
23. Bends use mitered or curved corners. Right-angle bends add ~5–15 fF of excess capacitance; a 45° miter or a radius ≥ 3 × trace width keeps discontinuity below 0.1 dB.
24. Trace width transitions tapered. Any width change (e.g., IC pad to 50 Ω line) uses a linear taper whose length ≥ λ/10 at the highest frequency of interest.
25. Via transitions modeled. A signal via without nearby ground vias is an uncontrolled inductance. Place at least four ground vias within 15 mil (0.38 mm) of every RF signal via.
26. Stub lengths minimized. Back-drill or use blind vias to remove via stubs longer than λ/20; at 28 GHz, that threshold is about 8 mil (0.2 mm).
27. Characteristic impedance verified with EM simulation. Run a 2.5-D or 3-D EM check on at least one representative cross-section and one critical discontinuity. Tools like HFSS or ADS Momentum are standard for this step.
28. Insertion-loss budget closed. Sum trace loss (dB/inch from the laminate datasheet), connector loss, via loss, and filter loss; confirm the total stays within the link budget with margin.

Section 4 — Grounding and Return Paths (Points 29–36)

29. Via stitching pitch ≤ λ/20. At 10 GHz (λ₀ ≈ 30 mm), stitch ground vias every 1.5 mm or closer around RF sections. Refer to IPC-2141A for controlled-impedance ground plane guidance.
30. No return-path discontinuities at layer transitions. Every signal via that changes reference planes needs nearby stitching vias connecting those planes.
31. Ground plane pour connected to chassis. Define the grounding topology (single-point, multi-point, or hybrid) and mark it on the assembly drawing.
32. Thermal pads properly connected. Exposed-pad QFN and LGA packages need a via array (typically 4–9 vias, 10–12 mil diameter) to the ground plane for both thermal and RF grounding.
33. Split grounds, if used, bridged correctly. Analog/digital ground splits rejoin at a single, defined point under the ADC/DAC; RF ground is never split.
34. Guard rings around sensitive nodes. LNA inputs, VCO tanks, and crystal oscillators benefit from a grounded copper pour ring with stitching vias at ≤ λ/20 spacing.
35. Board edge ground metallization. Castellated or plated edge vias at ≤ 2 mm pitch suppress cavity modes between stacked boards and between the PCB and a metal housing.
36. Connector ground continuity. SMA, U.FL, and SMPM footprints must have ground pads tied to the plane with multiple vias directly at the pad—not routed traces.

Section 5 — Component Placement and Selection (Points 37–42)

37. RF path is the shortest path. Place components so the RF signal flows in a straight or gently curving line with no backtracking.
38. High-gain and low-level stages separated. Keep PA output at least 10× the free-space wavelength away from LNA input to avoid feedback coupling. Use radiated emission control techniques if distance alone is insufficient.
39. Component body orientation consistent. Align passives so pick-and-place nozzle changes are minimized; this reduces placement time and cost.
40. Decoupling caps placed on the return-path side. A bypass cap on the opposite side of the board from the IC is acceptable only if a via connects it directly to the IC’s ground pad.
41. SRF and Q verified for every RF passive. A 100 pF 0402 cap with an SRF of 1.2 GHz is useless as a DC block at 2.4 GHz. Consult RF component selection guidelines for choosing the right package and value.
42. Thermal derating checked. Power amplifiers dissipating > 1 W need thermal-via arrays and possibly exposed copper on the outer layer for heatsinking.

Section 6 — EMC and Isolation (Points 43–48)

43. Clock harmonics mapped against RF bands. A 25 MHz crystal’s 96th harmonic lands at 2.4 GHz; route clocks on inner stripline layers, never microstrip.
44. Shielding cans specified. Define can footprint, height, and grounding method (solder or spring-clip) on the assembly drawing; partition TX, RX, and LO sections.
45. Creepage and clearance per IPC-2221B. For mixed-voltage boards (e.g., 28 V PA supply next to 1.8 V LNA), verify minimum spacing at the actual altitude and pollution degree.
46. ESD protection on external ports. TVS diodes or ESD clamps on antenna feeds and test ports; choose devices with capacitance < 0.5 pF for ports above 1 GHz.
47. Digital switching noise filtered at source. Ferrite beads or LC pi-filters on DCDC converter outputs before they reach the RF supply rail.
48. Radiated emission pre-scan estimated. If regulatory compliance is required (FCC Part 15, ETSI EN 301 489), budget a pre-compliance scan before layout freeze.

Section 7 — DFM, DFT, and Assembly (Points 49–54)

49. Minimum trace/space meets fab capability. Most RF fabs hold 3.5 mil (89 µm) trace/space on standard processes; tighter geometries require advanced imaging and cost more.
50. Drill aspect ratio ≤ 10:1. A 10-mil via in a 100-mil board is at the limit; deeper boards need larger drills or sequential lamination.
51. Solder mask clearance on RF pads. Open solder mask (mask-defined pads) on RF traces and component lands to avoid Dk variation from mask material (Dk ≈ 3.3–3.8).
52. Panelization does not cut through RF ground. V-score or tab-route lines must not sever ground-plane copper that the RF circuit depends on.
53. Test coupons included. Add impedance test coupons (microstrip and stripline) per Altium’s impedance-controlled routing guide on the panel rail for TDR verification.
54. Fiducials and tooling holes placed. At least three global fiducials and two tooling holes for SMT placement accuracy; critical for 0201 and 01005 RF passives.

Section 8 — Supply Chain and Compliance (Points 55–58)

Before tapeout, verify that every material and component in the BOM meets your program’s compliance requirements. Two often-overlooked areas are conflict-mineral sourcing and kitting completeness.

Conflict Minerals Verification

If your product ships into the EU or falls under SEC disclosure rules, confirm that tin, tantalum, tungsten, and gold (3TG) in your PCB and components are sourced from certified smelters. Use the tool below to walk through the standard CMRT (Conflict Minerals Reporting Template) items for your RF board assembly.

A completed conflict-minerals check typically surfaces one or two suppliers who have not yet filed their CMRT. Flag these early—waiting until production creates a stop-ship risk that no amount of RF tuning can fix.

Kitting Completeness

An RF prototype build often stalls because a single 0.5 pF NPO cap or a specialty filter is missing from the kit. Walk through every BOM line against the kitting checklist below before releasing the order.

After running the kitting check, pay special attention to long-lead RF filters (SAW, BAW, ceramic) and MMIC amplifiers—these regularly carry 8–12 week lead times and are the most common cause of prototype delays. For a broader view of what to hand off to manufacturing, see the design transfer checklist.

55. Conflict minerals (3TG) status confirmed for all PCB materials and components.
56. RoHS / REACH compliance verified on BOM. Especially check solder alloy, surface finish, and any leaded-solder exemptions for RF connectors.
57. All components available and kitted. No TBD line items, no end-of-life parts without approved alternates.
58. Export control (ITAR/EAR) classification recorded. Millimeter-wave and phased-array designs may fall under ECCN 3A001; confirm before sharing files internationally.

Section 9 — Final Tapeout Sign-Off (Points 59–60)

59. DRC and ERC clean at final state. Zero errors, zero unresolved waivers. Any accepted deviation is documented with an engineering justification and a signature.
60. Gerber / ODB++ output verified. Open every layer in a standalone viewer (not the EDA tool that generated it). Confirm copper, mask, drill, and silkscreen align. Cross-check the RF PCB documentation package contents against the fab’s input checklist.

Printable Summary Table

FAQ

How early should I start the RF PCB design checklist?

Begin at schematic entry. Points 1–8 are schematic-level checks; catching a missing bias network or wrong S-parameter model here avoids a full layout respin.

Can I use this checklist for digital-heavy mixed-signal boards?

The grounding, EMC, and DFM sections apply broadly, but the transmission-line and material sections are specific to RF. For boards where the distinction matters, review the differences between high-frequency and high-speed design.

What is the most commonly missed item?

Return-path continuity at layer transitions (Point 30). Engineers route a beautiful 50 Ω trace, change layers, and forget the stitching vias that connect the two reference planes. The result is a resonant slot that radiates and degrades return loss.

Do I need EM simulation for every RF board?

Not necessarily for simple single-band designs below 3 GHz on well-characterized laminates. Above 6 GHz, or for any design with tight isolation or loss budgets, full-wave EM verification of critical structures is strongly recommended.

How do I adapt this checklist for 77 GHz automotive radar?

The same 60 points apply, but tolerances tighten dramatically—via stubs must be back-drilled to < 4 mil, Dk tolerance drops to ±0.02, and surface roughness becomes a dominant loss factor. See the dedicated radar design review checklist for mmWave-specific additions.