Doherty Amplifier PCB Design for 5G PA Boards

What Is a Doherty Amplifier PCB?

A Doherty amplifier PCB is a printed circuit board engineered to implement the Doherty power amplifier topology, where a carrier amplifier and a peaking amplifier share a common load through a quarter-wave impedance inverter. This architecture delivers 10–15 percentage points higher average efficiency than a conventional Class AB PA when amplifying high peak-to-average-power-ratio (PAPR) signals such as 5G NR OFDM waveforms with 8–12 dB PAPR. The PCB itself is the performance-critical element: it must realize precise impedance networks, manage substantial heat flux from GaN or LDMOS devices, and maintain phase coherence across the carrier and peaking paths from sub-6 GHz bands up through 3.5 GHz and beyond.

Because the Doherty combiner is a distributed network whose electrical length must be exactly λ/4 at the design frequency, every aspect of the board—dielectric constant tolerance, copper roughness, via transitions, and thermal vias under the device flanges—directly affects efficiency, linearity, and reliability. This guide walks through the substrate, layout, thermal, and fabrication decisions that separate a mediocre Doherty amplifier PCB from one that meets a 5G base-station specification.

Why the Doherty Topology Dominates 5G PA Design

Modern 5G macro and small-cell base stations transmit wideband OFDM signals whose instantaneous power spends most of its time 6–10 dB below the peak. A conventional Class AB amplifier reaches peak drain efficiency only at saturation; at 6 dB output back-off (OBO) its efficiency roughly halves. The Doherty architecture solves this by load-modulating the carrier amplifier: at back-off the carrier sees a higher impedance and stays efficient, while the peaking amplifier turns on only near saturation to restore full power capability.

In practice, a well-executed two-way symmetric Doherty achieves 45–55 % drain efficiency at 6–8 dB OBO in the 3.4–3.8 GHz n78 band using GaN HEMT devices. Asymmetric and three-way Doherty variants push the efficiency plateau deeper, to 8–10 dB OBO, at the cost of greater PCB complexity. For the PCB designer, the implication is clear: the board must preserve the theoretical load-modulation behavior by keeping insertion loss low, phase balance tight (< 2° across the signal bandwidth), and thermal resistance under the transistors consistent between the carrier and peaking paths.

Substrate Selection for Doherty Amplifier PCBs

High-Frequency Laminate Options

The quarter-wave inverter and matching networks are sensitive to the dielectric constant (Dk) and dissipation factor (Df) of the substrate. A lower Df means less energy is wasted as heat in the laminate itself—critical when the combiner carries tens of watts of RF power. The table below compares substrates commonly used in Doherty amplifier PCBs for the 1.8–3.8 GHz cellular range.

For most sub-6 GHz Doherty amplifier PCBs, Rogers RO4350B offers the best balance of RF performance, thermal conductivity, and compatibility with standard FR-4 fabrication processes. When the design budget allows and insertion loss must be minimized (e.g., for massive-MIMO remote radio heads where every 0.1 dB matters), RO3003 or Astra MT77 is the better choice. For deeper discussion of substrate and thermal carrier considerations for high-power RF boards, see the RF power amplifier PCB design guide.

Dk Tolerance and Phase Accuracy

A quarter-wave line at 3.5 GHz on RO4350B (Dk = 3.48) is approximately 12.5 mm (492 mil) long. A ±0.05 variation in Dk shifts the effective electrical length by roughly ±0.7 %, which at 3.5 GHz translates to about ±1.3° of phase error. That is acceptable for a two-way Doherty, but in a three-way design where two inverters cascade, the errors compound. Specifying tighter Dk tolerance lots or selecting laminates with ±0.03 tolerance prevents efficiency droop from phase imbalance.

Layout of the Impedance Inverter and Combiner Network

Quarter-Wave Inverter Geometry

The Doherty combiner’s core is a λ/4 transmission line that transforms the carrier amplifier’s load impedance during load modulation. For a symmetric two-way design at 50 Ω system impedance, the inverter’s characteristic impedance is 50 Ω (sometimes 35.35 Ω for optimum load modulation, depending on the design variant). The line width and length must be calculated for the specific substrate thickness and Dk, accounting for copper roughness and solder-mask loading.

Key layout rules for the inverter:

• Keep the inverter straight or use gentle bends (radius ≥ 3× line width). Sharp 90° bends introduce parasitic capacitance that shifts the electrical length and degrades phase accuracy.
• Maintain continuous ground plane beneath the inverter. Any slot or via anti-pad under the microstrip line changes the effective Dk locally and creates an impedance discontinuity.
• Match the physical symmetry between carrier and peaking paths. Even if the peaking path includes an offset line for phase alignment, the ground-plane copper fill, via density, and solder-mask openings should mirror the carrier side to equalize parasitic loading.
• Use electromagnetic (EM) simulation—not just a line calculator—for the final dimensions. Coupling to adjacent structures, solder-mask dielectric loading (typically adding 0.5–1.0 to the effective Dk at the surface), and copper roughness (particularly on electrodeposited foil) can shift the inverter impedance by 1–3 Ω and the phase by 2–5°.

Input Splitter and Phase Compensation

The input power splitter divides the signal into carrier and peaking paths, often with a 90° phase offset so the peaking device sees the correct load at turn-on. Hybrid couplers (Lange or branch-line) are common at frequencies above 2 GHz; at lower frequencies, Wilkinson dividers with an external phase-offset line are more area-efficient. The splitter’s amplitude balance should be within ±0.3 dB and phase balance within ±2° across the instantaneous bandwidth (typically 100–400 MHz for a 5G NR carrier).

Designers working on phased-array or beamforming front-ends that integrate Doherty PAs per element face an additional constraint: the splitter must not radiate, or it will couple into adjacent channels. Shielding cavities or stripline construction may be necessary. Related layout techniques are discussed in the beamforming PCB design context.

Thermal Management on Doherty Amplifier PCBs

Heat Flux Under GaN and LDMOS Devices

A 100 W peak-power GaN HEMT operating at 50 % drain efficiency dissipates roughly 50 W as heat through its flange, concentrated in an area of approximately 10 × 5 mm. That is a heat flux of 100 W/cm²—comparable to a CPU die. In a Doherty PA, the carrier amplifier runs continuously while the peaking amplifier cycles; this asymmetric thermal loading can warp the board if not managed symmetrically.

Thermal via arrays under each transistor flange are the primary conduction path from the top copper pad to a heat-spreading layer or metal-core substrate beneath. Best practice:

• Via diameter: 0.3 mm (12 mil), plated with ≥ 25 µm copper fill or solid copper plugs.
• Via pitch: 0.8–1.0 mm (31–39 mil) center-to-center, giving 40–60 vias under a typical GaN flange.
• Thermal via fill: copper-filled and capped vias provide 3–5× lower thermal resistance than open or epoxy-filled vias.
• Board-to-heatsink interface: solder-attach the PCB to a CuMo or CuW carrier, or use a high-conductivity thermal interface material (TIM) with < 0.1 °C·cm²/W thermal resistance.

For Doherty amplifier PCBs above 200 W combined output, a metal-backed or coin-inserted construction (a copper or CuMo slug embedded in the PCB under the device) reduces the junction-to-case thermal resistance by 30–50 % compared to a via-only approach. This technique is standard in satcom and aerospace RF PCBs and translates directly to high-power terrestrial base-station PAs.

Thermal Symmetry Between Carrier and Peaking Paths

Because the carrier amplifier runs hotter on average, its bias point drifts differently from the peaking amplifier over temperature. If the PCB’s thermal paths are asymmetric—for example, the carrier side is closer to a board edge with less copper fill—the resulting gain and phase drift degrades the Doherty load-modulation and drops efficiency. The remedy is to mirror the thermal via pattern, copper fill area, and heatsink contact geometry for both devices, even though the peaking amplifier dissipates less average power.

Bias Network and Decoupling Layout

The drain bias network for each transistor must present a high impedance at RF frequencies while delivering DC current with minimal voltage drop. A typical approach uses a λ/4 high-impedance line (bias tee) followed by progressively larger decoupling capacitors: 10 pF → 100 pF → 1 nF → 100 nF → 10 µF. Layout pitfalls to avoid:

• Grounding the decoupling capacitors through long traces or shared vias. Each capacitor’s ground return must be a short, dedicated via to the ground plane directly beneath it. A shared via adds inductance that creates a resonance and can destabilize the amplifier.
• Running the bias line parallel to the RF path. Coupling between the bias tee and the output matching network creates a feedback path that degrades AM-PM linearity. Maintain ≥ 3× line-width separation or use orthogonal routing.
• Ignoring the video bandwidth. Digital pre-distortion (DPD) corrects PA nonlinearity only if the bias network’s baseband impedance is low out to 200–400 MHz. Insufficient decoupling at video frequencies causes memory effects that DPD cannot fully linearize. This is a common root cause when a Doherty PA meets efficiency targets but fails ACLR specifications.

Fabrication and Assembly Considerations

Stackup Design

A typical Doherty amplifier PCB for sub-6 GHz uses a 2-layer or 4-layer stackup. A 2-layer board (RF laminate over metal carrier) is preferred for simplicity and thermal performance. When digital control, power management, or DPD feedback paths must be integrated, a 4-layer hybrid stackup places the RF matching and combiner on the top laminate layer, a solid ground plane on layer 2, digital routing on layer 3, and a second ground or power plane on layer 4. The RF laminate (e.g., RO4350B, 20 mil / 0.508 mm) is bonded to an FR-4 or low-cost core for the inner layers using a low-Df prepreg such as Isola Astra MT77 prepreg.

Impedance Control and Tolerances

Specify controlled impedance on the inverter and matching lines with a tolerance of ±5 % or tighter. For a 50 Ω microstrip on 20 mil RO4350B, the trace width is approximately 1.1 mm (43 mil); a ±5 % impedance tolerance requires the fabricator to hold width within ±0.05 mm (±2 mil). Request a test coupon with TDR verification on every panel. The IPC-6012 Class 3 performance specification is the minimum reliability tier for telecom-grade Doherty PA boards; Class 3A applies for aerospace or defense deployments.

Surface Finish

ENIG (Electroless Nickel Immersion Gold) is the default surface finish for Doherty amplifier PCBs because it provides a flat, solderable surface for the GaN/LDMOS flange and wirebond or solder-attach pads. However, the nickel layer (typically 3–6 µm) is ferromagnetic and slightly lossy at microwave frequencies. For designs above 6 GHz or where every 0.05 dB of combiner loss matters, ENEPIG (adding a palladium barrier) or immersion silver may be preferable. Immersion silver has the lowest RF loss but requires careful handling to avoid tarnish before assembly.

Measurement and Validation on the PCB

After assembly, validate the Doherty amplifier PCB with these key measurements:

1. Small-signal S-parameters: Verify gain flatness (±0.5 dB) and input return loss (> 15 dB) across the design bandwidth using a VNA. Compare carrier-path and peaking-path S21 phase to confirm the λ/4 offset is within ±3°.
2. Load-pull at the board level: Use a passive or active load-pull setup to verify the Doherty load-modulation trajectory. The carrier device should see approximately 2× the optimum load impedance at 6 dB OBO.
3. CW and modulated power sweep: Measure drain efficiency versus output power. A healthy two-way GaN Doherty at 3.5 GHz should show an efficiency peak near saturation (60–70 %) and a second plateau at 6 dB OBO (45–55 %). If the OBO plateau is absent or weak, suspect phase or impedance error in the combiner.
4. ACLR with DPD: Apply a 5G NR 100 MHz OFDM signal and engage DPD. Target ACLR of –50 dBc or better at the rated average power. Poor ACLR despite good efficiency points to memory effects—revisit the bias decoupling network.
5. Thermal imaging: Run the PA at rated average power for 30 minutes and capture a thermal image. Confirm that the carrier and peaking device temperatures are within 10 °C of each other and that no hot spots appear on the combiner traces (which would indicate unexpected resistive loss).

For the receive chain on the same platform, low-noise amplifier PCB design follows complementary principles—minimizing noise figure rather than maximizing efficiency—but shares the same substrate and thermal-management toolkit.

Common Pitfalls and How to Avoid Them

• Using FR-4 for the combiner network. FR-4’s Dk varies ±10 % lot-to-lot and its Df of 0.02 at 3.5 GHz wastes roughly 0.3–0.5 dB in a λ/4 line. That loss directly subtracts from the efficiency advantage the Doherty topology provides. Always use a controlled-Dk RF laminate for the combiner.
• Neglecting solder-mask effects on impedance. Solder mask over the inverter line raises the effective Dk and lowers the impedance by 1–3 Ω. Either model the mask in EM simulation or specify solder-mask openings (windows) over all critical RF traces.
• Under-sizing the output combining node. The junction where the carrier and peaking paths merge carries the full combined current. If the copper area or via count at this node is insufficient, resistive loss and electromigration risk increase. Treat this node like a power bus junction: wide copper, multiple vias, and thermal relief only where soldering demands it.
• Ignoring the off-state impedance of the peaking amplifier. When the peaking device is off, its output capacitance (Cds) presents a reactive load at the combining node. If the offset line between the peaking device and the combiner does not transform Cds to an open circuit at the node, the carrier amplifier’s load modulation is corrupted. This offset line length is a critical layout dimension—simulate it with the actual device model, not an ideal open.

Frequently Asked Questions

What frequency range suits a Doherty amplifier PCB?

Doherty amplifier PCBs are most common from 700 MHz to 6 GHz, covering LTE and 5G NR sub-6 GHz bands. Above 6 GHz, the quarter-wave lines become very short and fabrication tolerances tighten; MMIC-based Doherty implementations on GaAs or GaN die are more practical at mmWave frequencies.

Can I use a standard FR-4 PCB for a Doherty PA?

FR-4 is unsuitable for the combiner and matching networks due to its high loss tangent (Df ≈ 0.02) and poorly controlled Dk. However, FR-4 can be used for non-RF layers in a hybrid stackup—digital control, power distribution, and DPD feedback routing—bonded beneath an RF laminate top layer.

How does the Doherty PCB differ from a balanced amplifier PCB?

A balanced amplifier uses two devices in quadrature to improve input/output match and gain flatness, but both devices operate identically—there is no efficiency advantage at back-off. A Doherty amplifier biases the carrier and peaking devices differently and uses load modulation to maintain efficiency at back-off. The PCB for a Doherty PA requires tighter phase control of the combiner and asymmetric bias networks, whereas a balanced PA PCB prioritizes coupler balance and broadband match.

What is the typical layer count for a Doherty amplifier PCB?

Most standalone Doherty PA modules use a 2-layer board (RF layer + ground) mounted on a metal carrier. Integrated radio units that combine the PA with digital processing may use 4–6 layers, with the top RF laminate layer dedicated to the Doherty matching and combiner networks. A broader look at layer-count decisions across different RF PCB application categories can help contextualize where the Doherty PA sits in complexity.

How tight must the phase balance be between carrier and peaking paths?

For a two-way Doherty at sub-6 GHz, keep the carrier-to-peaking phase error below ±3° across the instantaneous bandwidth (typically 100–400 MHz). Exceeding ±5° measurably degrades the efficiency plateau at OBO and can shift the ACLR by 2–3 dB, making DPD correction harder.