SIW Calculator: Cutoff, Width & Via Pitch

What Is a Substrate Integrated Waveguide?

A substrate integrated waveguide (SIW) is a planar waveguide built entirely inside a PCB stackup. Two rows of metallized vias connect the top and bottom copper planes, forming sidewalls that confine electromagnetic energy the same way a conventional rectangular waveguide does—but in a structure you can etch, drill and laminate with standard PCB processes. An SIW calculator takes the physical via-row spacing, via diameter, via pitch and substrate Dk, then returns the equivalent width and TE₁₀ cutoff frequency so you can verify single-mode operation before committing to layout. The dominant mode is TE₁₀, and the cutoff frequency depends on the via-to-via center spacing across the width, the via diameter, the via pitch along the propagation direction, and the substrate dielectric constant (Dk).

SIW lines are widely used from Ku-band (12 GHz) through W-band (110 GHz) in radar front-ends, satellite feeds, 5G mmWave filters and antenna feed networks. They offer lower radiation loss than microstrip at millimeter-wave frequencies, self-shielding, and easy integration with planar circuits—at the cost of larger footprint than microstrip and tighter drilling tolerances.

Key SIW Calculator Parameters

Equivalent Width (a_eff)

The physical center-to-center distance between the two via rows is a. Because the vias are discrete posts, not a continuous wall, the effective waveguide width is narrower. The most-cited closed-form correction, from Cassivi et al. (2002), is:

a_eff = a − d² / (0.95 · p)

where d is the via diameter and p is the longitudinal via pitch (center-to-center spacing along the propagation axis). This equivalent width maps the SIW directly to a dielectric-filled rectangular waveguide of width a_eff.

TE₁₀ Cutoff Frequency

Once you have a_eff, the TE₁₀ cutoff frequency is:

f_c = c / (2 · a_eff · √Dk)

where c is the speed of light (≈ 3 × 10⁸ m/s) and Dk is the relative permittivity of the substrate. For a 24 GHz automotive radar SIW on Rogers RO3003 (Dk 3.00), a typical a_eff of about 4.3 mm gives f_c ≈ 18.0 GHz—placing the operating band well above cutoff in the recommended 1.25 f_c to 1.9 f_c single-mode window.

Via Diameter and Via Pitch Rules

Two constraints keep radiation leakage through the via fence acceptably low:

• p / d ≤ 2.5 — the pitch-to-diameter ratio. Exceeding this lets significant energy leak between posts.
• d / λ_g < 0.2 — via diameter relative to the guided wavelength, ensuring each post behaves as a smooth wall segment rather than a scatterer.

In practice, a pitch-to-diameter ratio near 2.0 is a safe starting point. For a 0.4 mm (≈ 16 mil; 1 mil = 0.0254 mm) via drill, that means p ≈ 0.8 mm. Tighter pitches reduce leakage further but increase drill count, cycle time and cost. The via inductance calculator can help you verify that each post’s parasitic inductance stays low enough for the intended frequency.

SIW Calculator: Cutoff and Via Pitch

Enter your substrate Dk, the physical via-row spacing a, via diameter d, and longitudinal pitch p. The tool returns the equivalent width, TE₁₀ cutoff frequency, recommended single-mode bandwidth, and a pass/fail check on the p/d leakage rule.

For example, with Dk = 3.48 (RO4350B), a = 5.2 mm, d = 0.3 mm and p = 0.7 mm, you get a_eff ≈ 5.01 mm, f_c ≈ 16.1 GHz, and a single-mode window of roughly 16.1–30.5 GHz—ideal for a Ku/K-band filter. The p/d ratio of 2.33 passes the ≤ 2.5 rule, but tightening to p = 0.6 mm (ratio 2.0) would cut leakage loss by roughly 3–5 dB/λ_g at the upper end of the band. If the result shows a cutoff that is too high, increase a or choose a higher-Dk laminate; if cutoff is too low, narrow the waveguide or switch to a lower-Dk substrate.

Choosing the Right Substrate

SIW performance hinges on the laminate. Low dissipation factor (Df) reduces conductor-adjacent dielectric loss, which dominates at millimeter-wave frequencies. Tight Dk tolerance (± 0.02 or better) keeps the cutoff frequency where you designed it across a production lot.

Higher Dk shrinks the SIW cross-section (useful for compact designs) but narrows the single-mode bandwidth in absolute GHz. Lower Dk gives a wider bandwidth window and lower dielectric loss but demands a physically wider waveguide. For a deeper look at how Df drives insertion loss, try the dielectric loss calculator.

Loss Mechanisms in SIW

Conductor Loss

At millimeter-wave frequencies, current crowds into a thin skin depth on the top and bottom copper planes. On standard 1 oz (35 µm) copper at 60 GHz, the skin depth is only about 0.27 µm, so surface roughness matters enormously. An Rz roughness of 3 µm on standard electrodeposited copper can add 1–2 dB/cm of excess loss compared to rolled-annealed foil. Use the copper roughness loss calculator to quantify the Huray or Hammerstad correction for your foil choice, and the skin depth calculator to see how the penetration depth shrinks with frequency.

Dielectric Loss

Dielectric loss scales linearly with frequency and Df. At 77 GHz on RO3003 (Df 0.0013), dielectric loss in a typical SIW is on the order of 0.15–0.25 dB/cm—tolerable for short feed networks but significant over a 2 cm run. Switching to RT/duroid 5880 (Df 0.0009) cuts that roughly in half.

Radiation (Leakage) Loss

Radiation through the via fence is the loss mechanism unique to SIW. Keeping p/d ≤ 2.0 and d small relative to λ_g makes leakage loss negligible compared to conductor and dielectric loss across most designs. If your SIW calculator result shows a p/d ratio above 2.5, tighten the pitch or increase the drill diameter before proceeding.

Via Fabrication and Tenting for SIW

SIW via rows are mechanically drilled, laser drilled, or a combination. For vias ≥ 0.2 mm (8 mil), mechanical drilling is standard and cost-effective. Below 0.2 mm, laser drilling or sequential lamination may be needed, increasing cost significantly.

After drilling, the vias must be plated to form a continuous copper barrel. Minimum plating thickness per IPC-6012 Class 3 is 25 µm (1 mil) of copper in the barrel. For SIW, uniform plating is critical—thin spots create local impedance discontinuities that scatter energy and raise loss.

Once drilled and plated, you need to decide whether to tent, plug, or leave the vias open. Tented vias (covered with solder mask) keep solder out during assembly and protect the barrel, while plugged-and-capped vias allow via-in-pad placement for compact transitions. Use the selector below to pick the right treatment for your SIW vias and any signal vias on the same board.

For a typical 24 GHz SIW fence using 0.3 mm vias on a 0.508 mm thick laminate, the tool will recommend standard LPI solder-mask tenting—the most cost-effective option since these vias carry no component pads and the aspect ratio (roughly 1.7:1) is well within tenting limits. If you are also routing a coplanar-to-SIW transition with a via-in-pad launch, those specific vias should be plugged with conductive or non-conductive fill and capped, so the pad stays flat for reflow soldering. Choosing the wrong treatment can trap outgassing under reflow, causing solder voids on adjacent pads, so always confirm the via diameter and board thickness against the tenting capability of your fabricator’s solder-mask process.

SIW Design Checklist

1. Set your operating band. Define f_low and f_high. Ensure f_low ≥ 1.25 × f_c and f_high ≤ 1.9 × f_c for single-mode TE₁₀ operation.
2. Choose a substrate. Balance Dk (size), Df (loss), thickness (bandwidth and coupling), and cost.
3. Calculate a_eff and a. Use the SIW calculator above. Work backward from the desired f_c to find the physical via-row spacing.
4. Set via diameter and pitch. Target p/d ≤ 2.0 for low leakage. Verify d/λ_g < 0.2.
5. Estimate total loss. Sum conductor, dielectric and leakage contributions per unit length. Budget ≤ 0.5 dB for short interconnects; plan amplification or lower-loss materials for longer runs.
6. Design transitions. Microstrip-to-SIW tapered transitions are the most common; a quarter-wave transformer section can match impedance at the launch point.
7. Verify with 3-D EM simulation. The closed-form equations are accurate to within a few percent, but slot filters, bends and T-junctions inside SIW need full-wave analysis.

Frequently Asked Questions

What frequency range works for SIW on PCB?

SIW is practical from roughly 10 GHz up to 110 GHz on standard PCB processes. Below 10 GHz the waveguide width becomes impractically large (tens of millimeters); above 110 GHz, via drilling tolerances and plating uniformity become the limiting factors, and some designers move to air-filled waveguide or gap waveguide.

Can I build SIW on FR-4?

Technically yes, but FR-4’s high Df (0.020 at 10 GHz) and loose Dk tolerance (± 0.3 or more) make it a poor choice above about 6–8 GHz. The dielectric loss alone can exceed 1 dB/cm at 24 GHz. Low-loss PTFE or hydrocarbon laminates are strongly preferred.

How many vias are in a typical SIW?

It depends on the waveguide length and pitch. A 20 mm long SIW section with p = 0.7 mm has about 29 vias per row, so 58 vias total for the two sidewalls. Longer filter or feed-network structures can have hundreds of vias, which is why drill count and panel utilization matter for cost.

Does substrate thickness affect SIW cutoff?

Substrate thickness (height h) does not appear in the TE₁₀ cutoff equation—cutoff depends on width and Dk only. However, thickness affects the impedance of the TE₁₀ mode, coupling to higher-order modes, and the design of microstrip-to-SIW transitions.

What is the typical insertion loss of an SIW line?

On a low-loss laminate like RO3003 at 24 GHz, total SIW insertion loss is typically 0.2–0.4 dB/cm. At 77 GHz on the same material, expect 0.4–0.8 dB/cm, dominated by conductor and dielectric loss. Leakage is negligible when the via fence rules are met.