RF Power Integrity | PDN Design for PA & LNA

What Is RF Power Integrity and Why Does It Matter?

RF power integrity is the discipline of delivering clean, stable DC supply voltage to active RF stages—power amplifiers (PAs), low-noise amplifiers (LNAs), mixers and oscillators—with noise and ripple low enough that they do not degrade gain, noise figure or spectral purity. A PA drawing 2 A pulsed current from a 5 V rail can see tens of millivolts of IR drop and hundreds of millivolts of transient droop if the power-delivery network (PDN) is not designed with the same care as the signal path. That droop modulates AM-to-PM conversion, widens spectral regrowth, and in an LNA can raise the noise figure by a measurable fraction of a dB.

Unlike digital power integrity, where the primary concern is keeping voltage within a static tolerance window, RF power integrity must also suppress supply noise across a bandwidth that extends from DC through the modulation bandwidth and often up to the operating frequency itself. A 28 GHz PA with 800 MHz instantaneous bandwidth needs a PDN that is quiet from DC to at least 1 GHz—and ideally shows no resonant peaks all the way to the carrier.

PDN Impedance Targets for RF Stages

The fundamental rule is the same as in digital design: keep the PDN impedance below a target Z_target = ΔV / ΔI across the entire frequency range of interest, where ΔV is the maximum tolerable ripple and ΔI is the peak transient current. For a GaN PA on a 28 V rail drawing 4 A peak with a 50 mV ripple budget, Z_target = 0.05 / 4 = 12.5 mΩ. For a 3.3 V LNA with 80 mA current steps and a 5 mV budget (to protect noise figure), Z_target = 62.5 mΩ.

These targets must be met not just at DC but at every frequency where the stage draws dynamic current. In practice, three overlapping mechanisms share the job:

• DC to ~1 kHz: the voltage regulator’s output impedance and loop bandwidth.
• 1 kHz to ~100 MHz: bulk and mid-range decoupling capacitors.
• 100 MHz to several GHz: the PCB planes’ intrinsic capacitance and near-die ceramic capacitors (0201/01005 MLCCs with high SRF).

If any frequency band is left uncovered, a resonant peak in the PDN impedance profile will appear there, injecting supply noise at exactly that frequency into the active device.

IR Drop on Power Planes: The DC Foundation

Before worrying about GHz-range decoupling, get the DC voltage drop right. A 1 oz (35 µm) copper plane carrying 3 A through a 20 mm path that narrows to 2 mm at a via neck-down has a resistance on the order of 5–8 mΩ, producing 15–24 mV of IR drop—already a significant fraction of a tight ripple budget. Wider planes, heavier copper (2 oz / 70 µm), and shorter current paths all reduce this drop.

Use the calculator below to estimate the IR drop across your power plane for a given copper weight, path geometry and current. Enter your plane width, length, copper thickness and DC current.

If the tool returns, say, 18 mV for a 1 oz plane carrying 2.5 A over 15 mm at 3 mm width, that single segment already consumes more than a third of a 50 mV budget. The fix is straightforward: widen the pour to 6 mm (halving resistance), move the regulator closer to the PA, or step up to 2 oz copper on the power layer. In designs with GaN or GaAs PAs dissipating several watts, thermal relief patterns on the ground vias can also increase effective plane resistance—verify with a DC simulation, not just a rule of thumb.

Via Transitions and Current Bottlenecks

Every via transition between power layers adds roughly 0.5–1 mΩ per via (for a 0.3 mm drill in 1.6 mm board thickness). A single via feeding a PA pad at 3 A contributes only ~3 mV, but that via also adds inductance (~0.5–1 nH), which matters above 100 MHz. Use multiple vias in parallel—four to eight stitching vias under a PA’s thermal pad—to reduce both resistance and inductance. Place these vias directly under or immediately adjacent to the device pad, not offset by several millimeters through a trace.

Decoupling Strategy for PA and LNA Supplies

Capacitor Selection: SRF, ESR and Placement

Every MLCC has a self-resonant frequency (SRF) above which it behaves as an inductor. A 100 nF 0402 X7R capacitor typically resonates around 80–120 MHz; a 100 pF 0201 C0G part resonates near 1–2 GHz. Effective RF decoupling requires overlapping SRFs so that at least one capacitor in the network is capacitive at every frequency in the target range. A practical starting set for a 5 GHz PA supply might be:

C0G (NP0) dielectric is essential for the smallest values; X7R capacitors lose capacitance with DC bias and have higher ESR at RF, making them unsuitable as the last line of defense. Choosing the right RF component with adequate Q and SRF is as important as the value itself.

Layout: Shortest Loop Wins

A decoupling capacitor is only as good as its connection loop area. The current must flow from the power plane, through the via, through the capacitor, back through another via to the ground plane, and from the ground plane to the device ground. Every millimeter of trace and every unnecessary via adds inductance. Place the smallest-value capacitors within 1–2 mm of the device power pin, connected with short, wide traces (or direct pad-to-via connections) on the same layer as the device. The ground return via of each capacitor should land on a continuous ground plane directly below.

For LNA stages, where supply noise directly raises noise figure, consider a pi-filter topology: a small series resistor (1–10 Ω, or a ferrite bead rated for the DC current) flanked by shunt capacitors. This creates a low-pass filter that attenuates high-frequency noise from the upstream regulator. The penalty is a small DC voltage drop across the resistor—budget for it.

Ground Plane Integrity: The Other Half of the PDN

The return current for every RF signal and every supply transient flows through the ground plane. Slots, splits and gaps in the ground plane force return currents to detour, increasing loop inductance and creating common-mode noise that couples into sensitive stages. In RF boards, the ground plane beneath the signal layer should be unbroken and continuous, especially under PA and LNA footprints and their associated matching networks.

When multiple supply voltages require split power planes on an inner layer, route those splits so they never cross beneath an RF signal trace. If a split is unavoidable, stitch the ground plane on both sides of the split with closely spaced vias (λ/20 spacing at the highest frequency of concern) and add bypass capacitors across the gap. For boards operating above 10 GHz, even small ground-plane discontinuities can excite parallel-plate modes; consult an EM simulation setup to identify resonances before fabrication.

Signal Integrity Myths That Affect Power Integrity Decisions

RF engineers sometimes carry over rules of thumb from lower-frequency analog design that do not hold at microwave frequencies. For instance, the belief that “more decoupling capacitors are always better” can actually introduce anti-resonances between parallel capacitors, creating impedance peaks worse than having fewer, well-chosen values. Another common myth is that a solid copper pour automatically guarantees a low-impedance return path—it does not if the pour is poorly stitched or if the via field creates a Swiss-cheese pattern that raises sheet inductance.

Test your assumptions about signal and power integrity with the interactive tool below.

Understanding which rules are myths and which are physics helps you avoid over-designing the PDN (adding cost and board area) or under-designing it (losing performance). For a deeper look at where high-frequency and high-speed design rules converge and diverge, see the comparison of high-frequency versus high-speed design principles.

PDN Simulation and Measurement

Simulation

Modern PDN analysis tools (Ansys SIwave, Cadence Sigrity PowerSI, Keysight PathWave) can extract the impedance profile of a power-plane pair from DC to tens of GHz, including the effect of via transitions, plane shapes and mounted capacitors. The workflow is:

1. Import the layout (ODB++ or IPC-2581).
2. Assign port locations at each device power pin and at the regulator output.
3. Attach SPICE or Touchstone models for every decoupling capacitor.
4. Run a frequency-domain impedance sweep (typically 1 kHz to 10 GHz).
5. Compare Z(f) against the target impedance curve; iterate on capacitor values, placement and plane geometry until all peaks fall below the target.

For PA stages, also run a transient simulation using the device’s actual current waveform (from the datasheet or extracted from a load-pull model) to verify that voltage droop stays within spec during burst transmissions.

Measurement

On a fabricated board, measure PDN impedance with a VNA using a two-port shunt-through method (IEEE microwave measurement standards provide guidance on calibration). A pair of SMA probes or pogo-pin fixtures contact the power and ground planes near the device. The resulting S21 trace converts to impedance: Z = 25 / (10^(S21_dB/20)). Compare the measured profile against your simulation; discrepancies usually reveal missing capacitor models, unexpected plane resonances or poor via stitching.

Practical Layout Checklist for RF Power Integrity

Before sending your design to fabrication, walk through this checklist—or integrate it into your broader RF PCB design review checklist:

• IR drop budget: DC voltage at each device pin verified against minimum supply spec, accounting for copper weight, path width and via count.
• Decoupling cascade: At least three capacitor decades (µF, nF, pF) with overlapping SRFs covering DC to beyond the modulation bandwidth.
• Smallest cap closest: 100 pF C0G within 1–2 mm of the PA/LNA power pin; bulk caps can be further away.
• Ground plane continuity: No slots, splits or routing channels under active RF devices or their matching networks.
• Via stitching: Ground vias at λ/20 spacing around PA and LNA footprints; multiple parallel vias for power feed.
• Ferrite bead / R-C filter on LNA supply: Verified that the bead does not resonate in-band and that DC drop is acceptable.
• Thermal pad grounding: PA exposed pad connected to ground with an array of vias (≥4, ideally 8+), providing both thermal and electrical ground.
• Regulator placement: Linear regulator or LDO located within 15–20 mm of the PA; switching regulator output filtered before entering the RF section.

Special Considerations for mmWave and Wideband Systems

At millimeter-wave frequencies (24 GHz and above), the PDN’s parasitic inductance and plane resonances can couple directly into the RF path. A 1 nH parasitic on a bias line at 28 GHz presents about 176 Ω of impedance—effectively an open circuit that starves the device of current during fast transients. Designs targeting 77 GHz automotive radar or 5G FR2 bands need:

• Integrated bias tees with quarter-wave stubs or radial stubs on the RF layer, providing a low-impedance AC ground at the carrier while passing DC.
• Thin dielectric stackups (3–4 mil core under signal layers) to maximize plane capacitance and minimize via inductance.
• Low-loss laminates such as RO3003 or RO4835 on signal layers; the power-plane dielectric can be standard FR-4 since it carries only DC and low-frequency currents—but verify that the hybrid stackup does not introduce registration or lamination issues. Consult the RF PCB material selection guide for hybrid build-up options.

For more on layout rules specific to frequencies above 24 GHz, the mmWave PCB design guide covers trace geometry, transition design and grounding in detail.

Switching Regulators Near RF: Taming the Spurs

Switching converters are efficient but generate spurs at the switching frequency and its harmonics. A buck converter running at 2 MHz will produce tones at 2, 4, 6 MHz and so on, which can mix with the LO or modulation to create in-band interference. Mitigation strategies include:

• Distance and shielding: Place the switcher on the opposite side of the board from the RF section, with a ground-plane fence of stitching vias between them.
• Post-regulation: Follow the switcher with an LDO (low-dropout linear regulator) that has high PSRR at the switching frequency. Many modern LDOs from vendors like Texas Instruments offer >60 dB PSRR at 2 MHz.
• Spread-spectrum clocking: Some converters dither the switching frequency to spread spur energy, reducing the peak level by 10–20 dB. This trades a single sharp spur for a wider but lower noise pedestal—acceptable for wideband systems, but verify it does not raise the integrated noise floor in narrowband receivers.

Frequently Asked Questions

How much supply ripple can an LNA tolerate before noise figure degrades?

It depends on the device’s power-supply rejection ratio (PSRR), but as a practical guideline, keep ripple below 5 mV RMS on LNA supplies. Many GaAs and SiGe LNAs show measurable NF degradation (0.1–0.3 dB) with ripple above 10 mV in the 1–100 MHz range, where PSRR is falling.

Should I use a solid power plane or a wide trace for PA supply?

A solid plane offers the lowest impedance and the most return-current flexibility, but it can carry switching-regulator noise to sensitive areas. A wide trace (shaped pour) routed deliberately from regulator to PA gives you controlled impedance with less risk of coupling. For currents above 1 A, the pour should be at least 3–5 mm wide on 1 oz copper.

Do I need PDN simulation for every RF board?

For designs below 6 GHz with moderate PA currents (< 1 A), a careful hand calculation and good layout practice are often sufficient. Above 6 GHz, or whenever the PA draws pulsed currents above 2 A, a frequency-domain PDN simulation pays for itself by catching resonances that hand analysis misses.

Can FR-4 be used for power-plane dielectric layers in an RF board?

Yes. Power planes carry DC and low-frequency transient currents, so the higher Df of FR-4 (around 0.02 at 1 GHz) is irrelevant on those layers. Using FR-4 for inner power/ground cores while reserving Rogers or PTFE laminates for signal layers is a standard hybrid stackup strategy that reduces cost without sacrificing RF performance.

How close should the nearest decoupling capacitor be to the device pin?

The smallest-value bypass cap (typically 100 pF C0G) should be within 1–2 mm of the power pin, with its ground via landing on the reference plane directly below. Every additional millimeter of trace adds roughly 1 nH of loop inductance, which at 1 GHz is about 6 Ω—enough to defeat the purpose of the capacitor.