Altium RF Design Workflow: Impedance to Output

What the Altium RF Design Workflow Covers

Altium Designer handles RF PCB projects from schematic capture through impedance-controlled layout to Gerber and ODB++ output, but the default settings are built for digital boards. A reliable Altium RF design workflow adds three things the defaults lack: a stackup tied to real laminate data, constraint-manager rules that enforce controlled impedance and clearance on every RF net, and a verification loop that catches discontinuities before fabrication. This guide walks through each stage in the order you execute them.

Stage 1 — Stackup and Material Definition

Open the Layer Stack Manager before placing a single component. For RF work the stackup drives impedance, loss, and coupling, so it must reflect the actual laminate you intend to order. Key steps:

• Choose the laminate first. For designs below 6 GHz on a budget, a hybrid stackup with Rogers RO4350B (Dk 3.48 ± 0.05, Df 0.0037 at 10 GHz) on the RF layers and standard FR-4 on digital layers is a common compromise. For millimeter-wave work above 24 GHz, consider RO3003 or Megtron 7. Consult an RF PCB material selection guide to compare Dk tolerance, Df, and cost across laminates.
• Enter real dielectric data. In the Layer Stack Manager, set each dielectric layer’s thickness, Dk, and Df from the vendor datasheet at your operating frequency—not the generic 4.2 Altium pre-fills for FR-4.
• Define copper weights. Half-ounce (17.5 µm / 0.7 mil) finished copper is standard for fine-pitch RF traces; one-ounce copper is typical for power and ground planes. Enter these explicitly so the impedance solver uses the correct conductor thickness.
• Set the impedance profile. Use the built-in impedance calculator (or the field solver in Altium 24+) to target 50 Ω single-ended microstrip or grounded coplanar waveguide (GCPW). Record the solved trace width and gap—you will feed these into the constraint manager next.

The dielectric height between the signal layer and its reference plane is the single most sensitive variable in impedance control. Use the solver below to see how a ±0.5 mil (±12.7 µm) tolerance on that height shifts your impedance, then decide whether your fabricator can hold that tolerance or whether you need to widen your trace to desensitize the design.

For example, a 50 Ω microstrip on RO4350B with a 10 mil (0.254 mm) dielectric height needs roughly a 22 mil (0.56 mm) trace width. If the fabricator holds ±1 mil on the dielectric, impedance swings about ±2.5 Ω—acceptable for most 50 Ω systems. If tolerance is ±2 mil, the swing approaches ±5 Ω and you should discuss tighter laminate specifications or switch to GCPW, which is inherently less height-sensitive. For detailed GCPW design rules for millimeter-wave boards, see our dedicated guide.

Stage 2 — Schematic and Constraint Manager Rules

Schematic best practices for RF

Keep the schematic clean but information-rich. Assign net classes early: create at least RF_50Ω, RF_Diff, Power, and Digital. Annotate each RF net with its target impedance as a parameter so it propagates to the PCB and appears in the constraint manager without re-entry. Place decoupling capacitors on the schematic close to their associated IC pin so Altium’s room-based placement keeps them together during layout.

Constraint Manager setup

The Constraint Manager (or legacy Design Rules) is where Altium RF design rules become enforceable. Set up the following at minimum:

These rules map directly to the principles in setting up RF design rules in CAD. Altium’s DRC will now flag any trace segment that violates impedance or clearance, turning what used to be a review-meeting argument into an automated check.

Stage 3 — RF Layout Techniques in Altium

Component placement

Place the RF signal chain first—LNA, filter, mixer, PA—in a straight or gently curved path that minimizes total trace length. Keep the ground-return path short: every RF component pad that needs a ground via should have that via within 0.5 mm. Use Altium’s “Snap to Component Pad” and interactive length tuning to control electrical length on matching networks.

Trace routing

• Route RF traces on a single layer wherever possible; every via adds 0.1–0.3 nH of parasitic inductance and a small impedance discontinuity.
• Use smooth, radius-based bends (set the corner style to “Round” in interactive routing) rather than 45° miters. For frequencies above 10 GHz, miter or curved bends measurably reduce reflections.
• Stitch ground vias along both sides of a GCPW trace at a pitch ≤ λ/20 at your highest frequency. At 28 GHz (λ ≈ 10.7 mm in free space, shorter in dielectric), that means via pitch ≤ 0.4 mm.
• Understand the distinction between high-frequency and high-speed design—they share impedance control but diverge on loss budgets, shielding, and acceptable via counts.

Shielding and isolation

For on-board shielding, define keep-out regions and fence-via rows around sensitive RF blocks. Altium’s 3D body tool lets you model shield-can footprints so mechanical clearance is verified before ordering. The shield fence via pitch follows the same λ/20 rule as GCPW stitching vias.

Stage 4 — EM Verification and Co-Simulation

Altium alone does not include a full-wave EM solver, but its ecosystem supports two verification paths:

1. Built-in impedance/crosstalk analysis — adequate for straight transmission-line sections on well-characterized stackups. Run the impedance profile check on every RF net after routing.
2. Export to a 3D EM solver — for discontinuities (transitions, couplers, filters, antenna feeds), export the layout region as an ODB++ or STEP file and import it into HFSS or a Momentum-class solver. Simulate S-parameters across your band, then bring the touchstone (.s2p) file back into Altium’s simulation framework or your system-level tool.

This loop catches problems like a via transition that looked fine at 5 GHz but resonates at 24 GHz, or a filter stub whose effective length shifted because the etch compensation was wrong. Fix in layout, re-export, re-simulate—repeat until S11 and insertion loss meet spec.

Stage 5 — Manufacturing Output and Handoff

Generating correct output files is where many Altium RF designs lose quality. A disciplined output job should include:

• Gerber X2 (or ODB++) with all copper, mask, silk, and drill layers. Verify layer naming matches your fabricator’s convention.
• Impedance control table — a fabrication note listing every controlled-impedance net class, target impedance, tolerance, trace width, dielectric material, and reference layer. Altium’s Draftsman tool can auto-populate this from the stackup.
• Stackup drawing — exported from the Layer Stack Manager, showing material callouts (e.g., “Core 1: Rogers RO4350B, 10 mil, Dk 3.48 at 10 GHz”).
• Test coupon specification — request impedance test coupons on the panel edge so the fabricator can verify controlled impedance with TDR. See RF test coupon design for coupon types and placement rules.
• Pick-and-place and BOM — standard, but double-check that RF component orientations (especially directional devices like couplers and filters) are correct in the centroid file.

Before exporting, review Altium’s Constraint Manager documentation to confirm that every rule you set is actually being checked in the DRC pass—some impedance rules require the field solver to be enabled to report violations.

Altium RF Design Checklist

Use the interactive checklist below to walk through every critical gate from stackup definition through output. Check off each item as you complete it; anything left unchecked is a risk you are carrying into fabrication.

A completed checklist should show green on stackup definition, impedance rule assignment, DRC-clean routing, EM verification of critical structures, and output file review. If your EM verification box is unchecked because the schedule is tight, at minimum run the built-in impedance profile check and flag any net that deviates more than 5 % from target for post-fabrication TDR measurement. The checklist also serves as a handoff document—attach it to the design package so your fabricator and assembler know which steps were verified.

Common Pitfalls in Altium RF Design

• Using default Dk values. Altium pre-fills FR-4 at Dk 4.2, which is a 1 MHz value. At 5 GHz, most FR-4 grades measure closer to 4.0–4.1, and high-frequency laminates differ even more from their low-frequency numbers. Always enter frequency-specific Dk from the vendor datasheet.
• Ignoring etch compensation. The fabricator will etch traces narrower than your Gerber artwork. For 50 Ω microstrip at 5 GHz, a 1 mil over-etch shifts impedance roughly +1.5 Ω. Discuss etch compensation with your fabricator and, if needed, pre-compensate trace widths in the Altium rule.
• Placing ground vias too far from RF transitions. A via-less ground return under a component pad can add 0.5 nH or more, enough to degrade return loss above 3 GHz.
• Skipping the IPC-2141A cross-check. IPC-2141A provides formulas and design guidance for controlled-impedance RF circuits. Comparing your Altium solver results against IPC-2141A equations is a quick sanity check that catches stackup entry errors.

FAQ

Does Altium have a built-in EM solver for RF?

Altium Designer includes a 2D field solver for impedance and crosstalk estimation but not a full-wave 3D EM solver. For structures like via transitions, coupled-line filters, or antenna feeds, export the geometry to HFSS, CST, or ADS Momentum for rigorous S-parameter extraction.

Can I design millimeter-wave boards (above 24 GHz) in Altium?

Yes. Altium supports the fine trace widths (down to 3 mil / 75 µm) and via pitches needed for mmWave GCPW. The limitation is verification—you will need an external 3D solver to validate discontinuities at these frequencies, and your fabricator must support the tighter tolerances.

How do I set up differential RF impedance rules in Altium?

In the Constraint Manager, create a differential-pair rule scoped to your RF_Diff net class. Set the target differential impedance (commonly 100 Ω), the trace width, and the gap. Enable the coupled-microstrip or coupled-stripline model in the stackup’s impedance profile so the solver accounts for coupling.

What output format should I send to the fabricator for RF boards?

ODB++ is preferred because it embeds stackup, net, and impedance data in a single package. If your fabricator requires Gerbers, supplement them with a separate impedance control drawing and stackup PDF exported from Altium’s Draftsman.