LoRa PCB Design | 868 & 915 MHz Module Antenna Board

What Is a LoRa PCB and Why Does the Board Matter?

A LoRa PCB is the printed circuit board that carries a LoRa (Long Range) transceiver, its matching network, antenna feed and supporting power and digital circuitry. At 868 MHz (EU) and 915 MHz (US, AU), the free-space wavelength is roughly 345–328 mm (about 13 inches), so even a short trace mismatch or a poorly shaped ground plane can cost several dB of link budget — the difference between a 5 km and a 15 km range in real-world deployments. Getting the PCB right is the single highest-leverage step in any LoRa hardware project.

Key Frequency Bands and Regulatory Context

LoRa operates in license-free ISM bands defined by regional regulation. The two most common are the EU 863–870 MHz band (typically centered at 868 MHz) and the US 902–928 MHz band (centered at 915 MHz). Other regions use 433 MHz (Asia) or 923 MHz (AS923). Each band dictates antenna dimensions, filter requirements and maximum conducted power — usually +14 dBm ERP in Europe and +30 dBm EIRP in the US. Your LoRa PCB layout must support whichever band your product ships into, and dual-band 868/915 MHz designs are common for products sold globally.

Choosing Between a Module and a Discrete Transceiver

Most LoRa PCB designs start with a decision: use a pre-certified module (such as Semtech’s SX1276/SX1262-based modules from vendors like Murata, HopeRF or RAK) or lay down a bare transceiver IC with your own matching network and crystal. The table below summarizes the trade-offs.

For prototyping, proof of concept and low-to-medium volumes, a pre-certified module is almost always the right call. For high-volume IoT products (>50 k units/year) where BOM savings compound, a discrete design around the Semtech SX1262 transceiver is worth the engineering investment.

Antenna Options for a LoRa PCB

PCB Trace Antenna (Inverted-F or Meander)

A quarter-wave inverted-F antenna (IFA) etched directly on the PCB is the lowest-cost option. At 868 MHz the radiating element is roughly 82 mm long; at 915 MHz it is about 78 mm. The antenna requires a ground plane clearance area on the opposite side of the board — typically at least 30 × 40 mm kept free of copper — and its performance is sensitive to nearby plastic housings and batteries. Peak gain is usually –1 to +1 dBi. This is the most common choice for compact IoT sensor nodes.

Chip Antenna

Ceramic chip antennas (e.g., Johanson 0868AT, Abracon PRO-OB-471) occupy 7 × 3 mm or less but still need a ground-plane keep-out zone specified in the vendor datasheet — often 15 × 25 mm. Gain is typically –2 to 0 dBi. They simplify layout at the expense of a few dB of range.

External Antenna via U.FL or SMA Connector

For gateways, outdoor nodes and any design that needs >+2 dBi gain, an external antenna connected through a U.FL (IPEX) pigtail or a board-edge SMA is preferred. The PCB carries only a 50 Ω feed line from the transceiver to the connector. This gives the most flexibility and the best range, but adds cost and mechanical complexity.

Helical / Spring Antenna

A quarter-wave helical stub soldered to a pad is compact (~20 mm tall at 868 MHz) and cheap, but performance varies widely with manufacturing tolerance and proximity to the enclosure. Typical gain is 0 to +2 dBi in free space.

Impedance-Controlled Layout: The 50 Ω Path

Every millimeter of trace between the transceiver’s RF output and the antenna feed point must be a controlled-impedance 50 Ω transmission line. On a standard 1.6 mm, four-layer FR-4 stackup with a prepreg-to-ground spacing of 0.2 mm (about 8 mil), a microstrip trace width of roughly 0.35 mm (14 mil) gives 50 Ω at 900 MHz assuming a Dk of 4.3. These numbers shift with every stackup change, so always run your own impedance calculation for the actual laminate and layer spacing your fabricator provides.

A few non-negotiable layout rules for the RF path on a LoRa PCB:

• Keep the RF trace short. Every unnecessary millimeter adds loss and mismatch risk. Route the transceiver output to the antenna or connector in the shortest, straightest path possible — ideally under 15 mm.
• Maintain a continuous ground reference. The ground plane directly beneath the RF trace must be unbroken. No splits, no via stitching rows crossing under the trace, no signal routes on the ground layer in that zone.
• Use ground-stitching vias along both sides of the trace at intervals ≤ λ/20 (roughly 17 mm at 915 MHz) to suppress parallel-plate modes.
• Avoid sharp bends. Use 45° miters or smooth arcs; a 90° bend creates a capacitive discontinuity.
• Match pad transitions. Where the trace meets a component pad (PI network, balun, connector), taper the width smoothly or use the pad geometry recommended in the component datasheet.

These same controlled-impedance principles apply to higher-frequency RF boards such as 5G FR2 mmWave PCBs, though the tolerances at 28 GHz are far tighter than at 900 MHz.

Material Selection: FR-4 vs. High-Frequency Laminates

At 868–915 MHz, standard FR-4 (Dk ≈ 4.2–4.5, Df ≈ 0.018–0.025) is adequate for most LoRa PCB designs. The dielectric loss over a 10–15 mm trace at 900 MHz is well under 0.1 dB — negligible compared to the 1–2 dB typically lost in the matching network and connector. FR-4 is the default for cost-sensitive IoT hardware.

High-frequency laminates such as Rogers RO4350B (Dk 3.48, Df 0.0037) or Isola Astra MT77 become relevant only when:

• The PCB trace antenna is the sole radiator and every 0.1 dB of feed loss matters for range targets.
• The design shares a board with a higher-frequency radio (e.g., a combined LoRa + Wi-Fi 6E or LoRa + GNSS product).
• Temperature stability of Dk is critical — FR-4’s Dk can drift ±5 % over –40 to +85 °C, while RO4350B stays within ±1 %.

For the vast majority of LoRa nodes and gateways, FR-4 with a well-controlled stackup is the right choice. Spending budget on a better antenna or a low-noise LNA front end yields more range per dollar than upgrading the laminate.

Stackup and Layer Assignment

A four-layer stackup is the practical minimum for a LoRa PCB that carries both RF and digital circuitry. A recommended assignment:

The L1-to-L2 prepreg thickness controls the microstrip impedance. A 0.2 mm (8 mil) prepreg with Dk 4.3 is a common, widely available choice. Ask your fabricator for their standard controlled-impedance stackup options before locking the design — this avoids non-standard material upcharges.

Grounding and Power Decoupling

Poor grounding is the number-one LoRa PCB layout mistake. The transceiver’s ground pins (often an exposed pad) must connect to the L2 ground plane through multiple vias — at least four, placed directly under the pad. The matching network components likewise need short, via-connected ground returns.

Separate the digital and RF power domains with ferrite beads or small inductors (e.g., 10 nH in series) and place 100 nF + 1 µF decoupling capacitors within 1 mm of each VCC pin. Semtech’s reference designs for the SX1261/62 specify exact decoupling values and placements; follow them closely.

If your design includes a frequency synthesizer or PLL-based clock source, keep its supply filtering and loop filter components well away from the LoRa transceiver’s RF section to prevent spur coupling.

Matching Network Layout

Most LoRa transceivers require a simple PI or L-network between the RF pin and the antenna to transform the IC’s output impedance (often not exactly 50 Ω) to the antenna’s feed impedance. Typical component values are in the low-pF and low-nH range — 1.5 pF, 6.8 nH, 3.3 pF is a representative PI-match for an SX1276 at 868 MHz.

Layout rules for the matching network:

• Place all matching components on the same side of the board as the transceiver, in a straight line between the RF pin and the antenna feed.
• Use 0402 (1005 metric) or 0201 (0603 metric) passives to minimize parasitic inductance and pad capacitance.
• Ground pads of shunt capacitors connect to L2 through a via placed directly at the pad — not 0.5 mm away.
• Do not route any other signal under or adjacent to the matching network.

After assembly, verify the match with a VNA. A return loss better than –10 dB (VSWR < 2:1) across the operating band is the minimum target; –15 dB or better is achievable with careful layout.

Mixed-Signal Partitioning

A typical LoRa end-node PCB carries an MCU (STM32, nRF52, ESP32), sensors (I²C/SPI), a power management IC, a battery connector and the LoRa transceiver. Partition the board into zones:

• RF zone: transceiver, matching network, antenna or connector. No digital traces enter this zone.
• Digital zone: MCU, flash, sensor ICs, USB or UART headers.
• Power zone: regulator, battery charger, bulk capacitors.

The SPI bus between the MCU and the LoRa transceiver crosses the zone boundary. Keep these traces short (under 25 mm), route them over continuous ground, and add 33 Ω series resistors on MOSI and SCK to slow edges and reduce EMI. Similar mixed-signal discipline applies to software-defined radio boards where ADC and RF sections coexist.

Thermal and Mechanical Considerations

LoRa transceivers draw modest current — 120 mA peak TX for an SX1262 at +22 dBm — so thermal management is rarely a bottleneck. However, if a power amplifier (PA) is added for gateway use at +27 or +30 dBm, provide a thermal pad with multiple vias to an internal copper plane. Outdoor enclosures should account for the operating range of –40 to +85 °C specified by most LoRa ICs; choose a laminate Tg above 150 °C (standard FR-4 meets this) and ensure solder joints can handle thermal cycling per IPC-6012 Class 2 or Class 3 requirements depending on the application’s reliability tier.

Common LoRa PCB Mistakes That Kill Range

1. Ground plane void under the RF trace. Even a single signal via or trace crossing under the 50 Ω line creates a slot in the return-current path and radiates.
2. Antenna keep-out zone violated. Placing copper fill, traces or components inside the antenna’s specified clearance area detunes it and drops gain by 3–6 dB.
3. Wrong trace width. Designing for 50 Ω on a two-layer board with 1.6 mm substrate-to-ground spacing requires a trace roughly 3 mm wide — far wider than most designers expect. A four-layer board with a tight L1–L2 spacing solves this.
4. Long or meandered RF trace. Routing the RF path around other components adds loss and phase error. Prioritize the RF path first, then route everything else around it.
5. No impedance control in the fab spec. If you do not call out controlled impedance on the fabrication drawing, the manufacturer will not control it. Specify 50 Ω ± 10 % microstrip with a test coupon.

Design Checklist

• Band and region confirmed; antenna dimensioned for 868, 915 or dual-band.
• Stackup defined with fabricator; L1–L2 spacing and Dk confirmed; 50 Ω trace width calculated.
• Continuous ground plane on L2 under entire RF section — no splits, no crossings.
• Matching network laid out in-line, 0402 or smaller, shunt-cap vias at pad edge.
• Antenna keep-out zone respected on all layers.
• SPI and digital traces partitioned away from RF zone; series resistors on clock lines.
• Decoupling caps within 1 mm of every VCC pin; ferrite bead between digital and RF supply.
• Controlled impedance called out on fab drawing with test coupon.
• VNA verification planned for first article.

Frequently Asked Questions

Can I use a two-layer PCB for a LoRa design?

Yes, but with trade-offs. On a two-layer 1.6 mm FR-4 board the 50 Ω microstrip trace is about 3 mm wide, which is awkward for compact layouts. The ground plane is on the bottom layer, so every component via interrupts it. Two-layer LoRa boards work for simple, cost-driven designs if you keep the RF path very short and leave a solid ground pour beneath it.

What range can I expect from a well-designed LoRa PCB?

With a +14 dBm transmitter, a 0 dBi PCB antenna and a sensitivity of –137 dBm (SF12, 125 kHz BW), the link budget is 151 dB. In open rural terrain this translates to 10–15 km line-of-sight. In urban environments, expect 1–5 km depending on building density. A better antenna (+3 dBi external) or a gateway with a low-noise amplifier front end can significantly extend coverage.

Does the LoRa PCB need conformal coating for outdoor use?

For any outdoor or high-humidity deployment, conformal coating (acrylic or silicone, 25–75 µm thick) is strongly recommended. Keep the coating away from the antenna element and RF connector center pin to avoid detuning. IPC-CC-830C defines qualification tests for conformal coatings in electronics.

Should I use ENIG or HASL surface finish?

ENIG (Electroless Nickel Immersion Gold) is preferred for LoRa PCBs because it provides a flat, solderable surface for fine-pitch module pads and consistent impedance on RF traces. HASL is acceptable for prototypes but its uneven surface can shift impedance slightly on narrow microstrip lines.