Diplexer PCB Design: Layout, Materials & Filters

What Is a Diplexer PCB?

A diplexer PCB is a printed-circuit-board implementation of a three-port passive network that splits or combines two frequency bands through a common port while maintaining high isolation between the band ports. Unlike a simple power splitter, a diplexer uses frequency-selective filter sections—typically bandpass or low-pass/high-pass pairs—so each port passes only its intended band and rejects the other. Duplexers are a subset where the two bands correspond to transmit and receive paths in the same antenna system, demanding especially tight isolation (often > 40 dB) to protect the receiver.

Multiplexer boards extend the concept to three or more bands (triplexers, quadplexers). The PCB design principles are the same: each channel is a filter whose input connects at a common junction node, and the board must preserve filter performance while managing coupling, grounding, and transitions. This guide covers the layout, material, and fabrication decisions that make or break a diplexer PCB from UHF through 77 GHz.

Diplexer vs. Duplexer vs. Multiplexer: When Each Applies

All three share a common junction topology. The junction is the single most layout-sensitive point on the board: parasitic capacitance or extra line length here shifts every filter’s response. Design the junction first, then route each filter outward.

Filter Topologies Used on Diplexer PCBs

Coupled-Line Bandpass Filters

Edge-coupled microstrip or stripline sections are the workhorse of planar diplexers from about 800 MHz to 30 GHz. A typical third-order coupled-line bandpass filter occupies roughly λ/2 per resonator at center frequency, so a 2.4 GHz section on RO4350B (Dk 3.48) is about 38 mm long. Tighter coupling gaps (down to 100 µm / 4 mil) steepen the skirts but demand tighter fabrication tolerances. For deeper coverage of coupled-line and cavity filter fabrication, see the dedicated RF filter and duplexer PCB guide.

Stepped-Impedance and Hairpin Filters

When board area is limited, hairpin (folded half-wave) resonators cut length by roughly 40 %. Stepped-impedance resonators push spurious passbands higher, which matters when the two diplexer bands are close together and the upper filter’s second harmonic could leak into the lower band.

Low-Pass / High-Pass Complementary Pairs

Below 1 GHz, a diplexer is often a complementary LP/HP pair sharing a common node. The LP arm uses distributed or lumped-element low-pass sections; the HP arm uses series capacitors and shunt inductors. This topology is simpler to tune but offers less rejection per unit length than bandpass designs.

Substrate-Integrated Waveguide (SIW) Filters

Above 20 GHz, SIW cavity filters on low-loss laminates achieve unloaded Q values of 300–500, far exceeding microstrip resonators. Via fences form the waveguide walls; via pitch must stay below λ/10 at the highest frequency to prevent leakage. SIW diplexers are common in 24 GHz and 77 GHz automotive radar modules and in waveguide-to-microstrip transition boards.

Substrate Material Selection

Material choice controls insertion loss, frequency stability, and cost. The table below compares substrates commonly used for diplexer PCBs.

For diplexers above 10 GHz, loss tangent (Df) dominates insertion-loss budgets. A 24 GHz coupled-line BPF on RO4350B may show 1.8 dB insertion loss; the same geometry on RO3003 drops to about 0.9 dB. That 0.9 dB matters when the diplexer sits directly behind a low-noise amplifier in a radar receive chain. Consult the Rogers RO3000 series datasheet for detailed Dk vs. frequency curves.

PCB Layout Rules for Diplexer Performance

Junction Node Design

The common junction where both filters meet the antenna port must be as electrically small as possible. Any excess T-junction area adds shunt capacitance that detunes both filters. Practical guidelines:

• Keep the junction pad area below (λ/20)² at the higher band’s center frequency.
• Use a chamfered or curved T-junction to reduce the effective discontinuity capacitance.
• Place stitching vias within 200 µm (8 mil) of the junction on both sides to tighten the ground return.

Inter-Channel Isolation

Physical separation between the two filter arms is the first line of defense. A minimum gap of 3× the substrate thickness (3 h) between coupled-line sections of different filters keeps electromagnetic coupling below −50 dB in most microstrip designs. Where space is tight, a row of ground vias (via fence) between the arms adds 15–25 dB of additional isolation. For stripline implementations, continuous ground planes above and below inherently shield the filters, but shared via fields at the junction still need careful spacing.

Ground Via Strategy

Every shunt stub, SIW wall, and filter ground pad requires a low-inductance via connection to the reference plane. Via inductance is roughly 1 nH per millimeter of via length in a standard drill; at 10 GHz that is about 63 Ω of reactance, enough to shift a filter’s center frequency by several percent. Use back-drilled or blind vias to shorten the current path in thick multilayer stackups. Via diameter and pad size affect both impedance and drill-to-copper clearance—use the converter below to translate between drill specification units.

For example, a 10 mil (0.254 mm) finished drill with a 20 mil pad and 5 mil annular ring is a common choice for ground-stitching vias on diplexer boards up to 30 GHz. Above 40 GHz, laser-drilled microvias (4–6 mil / 0.10–0.15 mm) are preferred because their shorter barrel length cuts via inductance roughly in half.

Trace Width and Dimensional Tolerance

Coupled-line filters are sensitive to both trace width (W) and gap (S). A ±0.5 mil (±12.7 µm) variation in gap spacing on a 5 mil gap shifts coupling by roughly 1 dB, which directly impacts passband ripple and return loss. Specify IPC Class 3 artwork tolerances (±0.5 mil etch) or tighter for any diplexer above 5 GHz. Converting between mils and millimeters accurately matters when your EM simulator works in mm but your fab house quotes in mils.

Entering 5 mil returns 0.127 mm—confirm this matches the minimum gap your fabricator can hold at ±0.5 mil tolerance. If the fab can only guarantee ±1.0 mil, widen the coupling gap and compensate with longer coupled sections, accepting a slightly larger footprint.

Stackup Considerations

A typical diplexer PCB stackup for frequencies below 15 GHz uses four layers:

1. Layer 1 (top): Filter traces and junction—microstrip.
2. Layer 2: Continuous ground plane, no splits under filter traces.
3. Layer 3: DC bias, control lines, or a second ground for stripline filters.
4. Layer 4 (bottom): Ground or connector pads.

For duplexers requiring > 50 dB TX/RX isolation, place each filter on a different signal layer with a shared ground plane between them (embedded stripline). This adds a layer but the continuous copper between filters provides 20–30 dB of additional shielding compared to side-by-side microstrip.

At millimeter-wave frequencies (24–77 GHz), stackups often grow to six or eight layers to accommodate SIW cavities, DC distribution, and digital control—while keeping the RF layers on the outermost high-frequency laminate. Hybrid stackups bond a Rogers core to FR-4 prepreg for the non-RF layers, saving cost without compromising RF performance.

Simulation and Tuning Workflow

1. Synthesize filter prototypes from Chebyshev or elliptic response tables for each band. Target 0.5 dB excess insertion loss and 20 dB return loss as starting points.
2. EM-simulate each filter independently in a 2.5-D solver (e.g., Cadence AWR Microwave Office or Keysight ADS Momentum) on the exact stackup and material Dk/Df.
3. Combine at the junction and re-simulate the full three-port. Watch for junction-induced frequency shifts—typically 1–3 % downward due to added capacitance.
4. Optimize junction geometry (chamfer radius, stub offset) to recover center frequencies and restore port match.
5. Run a 3-D FEM simulation of the final layout including vias, connectors, and housing to capture any resonant cavity modes in the enclosure.
6. Verify on a test coupon. Fabricate a first-article board and measure S-parameters on a calibrated VNA. Use RF test fixtures with TRL calibration to de-embed connector effects.

Fabrication and Assembly Notes

• Surface finish: ENIG (electroless nickel immersion gold) is standard. For frequencies above 40 GHz, consider immersion silver or hard gold to avoid the 2–5 µm nickel barrier layer, which increases conductor loss at skin-depth scales.
• Solder mask: Keep solder mask off all coupled-line filter sections. Mask adds a dielectric layer (Dk ≈ 3.5–4.0) that shifts effective Dk and increases loss. Define mask-free zones (solder-mask-defined openings) around every resonator.
• Panel registration: Diplexer boards with tight coupled-line gaps benefit from laser direct imaging (LDI) rather than film-based exposure, improving registration to ±12 µm.
• Connector choice: SMA for prototype and bench work up to 18 GHz; 2.92 mm (K) connectors to 40 GHz; 1.85 mm (V) to 67 GHz. Edge-launch connectors with controlled-impedance footprints minimize the transition discontinuity. Ensure connector ground pins land on the same via row that stitches the filter ground.

Application Examples

Many of these systems also require phase-shifter PCBs and RF switch matrices alongside the diplexer, so designing a consistent stackup and ground strategy across the entire RF PCB application family saves integration headaches later.

Common Pitfalls and How to Avoid Them

• Ignoring junction parasitics: Simulating each filter alone and then connecting them in schematic gives an optimistic result. Always EM-simulate the physical junction.
• Ground plane splits under filters: Any slot or split in the reference plane beneath a resonator creates an unintended slot-line mode that radiates and couples to the other filter arm. Keep the ground plane continuous under all RF traces.
• Dk tolerance mismatch: Designing to nominal Dk without checking the vendor’s tolerance band leads to center-frequency surprises. A ±0.05 Dk spread on RO4350B shifts a 10 GHz filter by roughly ±70 MHz—acceptable for a 500 MHz bandwidth filter, risky for a 100 MHz one.
• Thermal drift in outdoor units: PTFE substrates exhibit a Dk temperature coefficient of about −100 ppm/°C. Over a −40 to +85 °C range, that is a 1.25 % Dk shift. Ceramic-filled laminates (RO3003, Astra MT77) cut this to roughly −30 ppm/°C. Budget for it or add post-fabrication tuning pads.

Design Checklist

1. Define band-edge frequencies, isolation, insertion-loss, and return-loss specs for each port.
2. Choose filter topology (coupled-line, hairpin, SIW) based on frequency, size, and Q requirements.
3. Select substrate with Dk tolerance ≤ ±2 % and Df appropriate for the loss budget.
4. Design junction geometry first; verify with EM simulation.
5. Route filter arms with ≥ 3 h separation or a via fence between them.
6. Remove solder mask from all resonator and coupled-line regions.
7. Specify IPC Class 3 etch tolerances (±0.5 mil) for gaps ≤ 8 mil.
8. Simulate full three-port including vias, connectors, and enclosure.
9. Fabricate first article; measure with calibrated VNA; correlate to simulation.

FAQ

Can I build a diplexer on standard FR-4?

Yes, for frequencies below about 1 GHz where FR-4’s high loss tangent (Df ≈ 0.020) and loose Dk tolerance (±10 %) are tolerable. Cable-TV diplexers splitting low-band (5–42 MHz) from high-band (54–1002 MHz) routinely use FR-4. Above 1 GHz, switch to a controlled-Dk laminate such as RO4350B.

How much isolation can a PCB diplexer achieve?

A well-designed microstrip diplexer with via fencing typically achieves 35–50 dB port-to-port isolation. Stripline or SIW implementations can reach 55–65 dB. If the system requires more, add an external circulator or isolator on the antenna port.

What is the difference between a diplexer and a duplexer on PCB?

Electrically, a duplexer is a diplexer whose two bands are the TX and RX frequencies of a single transceiver. The PCB difference is that duplexers face higher power on the TX arm (often 1–10 W) and need tighter isolation to protect the RX LNA, so trace widths, thermal relief, and shielding are more aggressive. Refer to IEEE MTT-S literature on microstrip duplexer design for measured isolation benchmarks.

Do I need back-drilling for a diplexer PCB?

Back-drilling (controlled-depth drilling to remove unused via stubs) is recommended for any diplexer above 10 GHz. A 1 mm via stub resonates near 37 GHz and can create a notch that lands inside your passband. Below 10 GHz, the stub effect is usually negligible unless the board is very thick (> 2.4 mm / 93 mil).

How do I handle mixed-signal layers in a diplexer board?

Keep digital and DC layers below the RF ground plane, never between RF signal layers and their reference. Use via fences around the RF section perimeter and avoid routing digital traces directly beneath filter resonators. A solid, unbroken ground plane between RF and digital layers is non-negotiable.