Impedance Test Service | TDR Report per Lot

What Is an Impedance Test Service?

An impedance test service measures the characteristic impedance of transmission-line traces on finished PCBs using time-domain reflectometry (TDR). The fabricator launches a fast-rise-time pulse into a dedicated test coupon, records the reflected waveform, and converts it to an impedance-versus-distance profile. Each production lot ships with a report proving every controlled-impedance net falls within the agreed tolerance—typically ±5 % for single-ended 50 Ω lines and ±10 % for differential 100 Ω pairs, following IPC-2141A guidelines.

If your board carries RF, high-speed serial or DDR signals, this per-lot verification is the only practical way to confirm that the stackup, etch factor and laminate Dk combined to hit the target. A controlled impedance PCB without a TDR report is an unverified claim.

How TDR Testing Works

The Pulse and the Reflection

A TDR instrument generates a voltage step with a typical rise time of 20–35 ps. When the step reaches an impedance discontinuity—trace-width change, via transition, or the coupon’s open end—part of the energy reflects back. The instrument plots reflected voltage against propagation time, which maps directly to physical distance along the trace. The characteristic impedance at any point equals Z₀ × (1 + ρ) / (1 − ρ), where ρ is the reflection coefficient at that location.

Test Coupons vs. In-Circuit Probing

Production impedance testing almost always uses dedicated coupons panelised alongside the working boards. Coupons replicate the exact trace width, copper weight, dielectric thickness and solder-mask coverage of the real nets but terminate in probe pads accessible to the TDR fixture. This avoids probing the product board and risking pad damage. Coupon designs follow IPC-2141A Appendix A, with separate structures for single-ended microstrip, single-ended stripline, edge-coupled differential microstrip and broadside-coupled differential stripline.

For a deeper look at reading TDR waveforms and spotting common artefacts, see our guide on TDR measurement basics.

What the Per-Lot Report Contains

A complete impedance test report typically includes:

• Lot and date code — ties the report to a specific production run.
• Coupon ID and layer reference — identifies which stackup layer each measurement represents (e.g., L1 microstrip, L3-L4 stripline).
• Target impedance and tolerance — the nominal value (50 Ω, 75 Ω, 90 Ω, 100 Ω differential, etc.) and the agreed window.
• Measured impedance — actual TDR reading for each coupon, usually three to five points along the trace length.
• Pass / fail verdict — per coupon and per lot.
• TDR waveform screenshot — the raw impedance-vs-distance plot, letting engineers see not just the average but any localised dip or spike.
• Instrument calibration date — confirms the TDR was calibrated within its interval, typically 12 months per ISO 17025.

Understanding how to audit these fields is covered in detail in our test report interpretation guide.

Tolerance Tiers and When to Tighten Them

Tighter tolerance costs more because the fabricator must narrow the etch and dielectric-thickness windows, often requiring a material with a more stable Dk. Rogers RO4350B (Dk 3.48 ± 0.05 at 10 GHz) holds impedance more predictably than standard FR-4 (Dk 4.2–4.6 depending on resin content and frequency). If your design demands ±5 % on stripline pairs, consult the RF PCB material selection guide before finalising the stackup.

Capacitance and Inductance per Unit Length

Characteristic impedance is fundamentally set by the distributed capacitance (C′) and inductance (L′) per unit length of the trace: Z₀ = √(L′ / C′). Understanding these two parameters helps you predict how stackup changes shift impedance before you even run a field solver.

Capacitance per Length

Capacitance per length rises when you move the trace closer to the reference plane, widen the trace, or increase the laminate Dk. Enter your trace geometry below to see C′ in pF/mm and judge whether your stackup leaves room for the target impedance.

For example, a 10 mil (0.254 mm) wide microstrip on 5 mil (0.127 mm) RO4350B typically shows roughly 1.2 pF/cm. If you switch to a 4 mil dielectric, C′ jumps to about 1.6 pF/cm, pulling impedance down by nearly 15 %. That shift will show up on the TDR report unless you compensate with a narrower trace.

Inductance per Length

Inductance per length depends mostly on trace height above the ground plane and trace width. A taller dielectric or narrower trace raises L′, pushing impedance up. Use the calculator below to estimate L′ in nH/mm.

A typical 50 Ω microstrip on the same RO4350B stackup shows L′ near 3.0 nH/cm. If your calculated Z₀ = √(L′ / C′) deviates from the target by more than a few percent, iterate the trace width before ordering—catching the mismatch at the design stage is far cheaper than failing the impedance test service at production.

Is an Impedance Test Necessary on Every Order?

For any board operating above a few hundred megahertz, or carrying high-speed serial lanes with eye-diagram specs, the answer is almost always yes. The incremental cost of adding TDR coupons and a per-lot test is small relative to the risk of shipping boards that degrade signal integrity. We discuss the edge cases—prototype-only runs, non-critical digital boards—in our article on whether an impedance test is necessary on every RF order.

Common Failure Modes Caught by TDR

• Over-etch — trace narrower than artwork, impedance reads high. Often worst on outer layers with aggressive cupric-chloride chemistry.
• Dielectric thickness drift — prepreg flow varies with press cycle; a 0.5 mil shift in core thickness can move impedance 3–4 %.
• Solder-mask loading — liquid photoimageable (LPI) mask adds 10–15 µm of dielectric with Dk ≈ 3.3–3.8, lowering microstrip impedance by 1–3 Ω. Coupons must be masked identically to the product trace.
• Resin-starved areas — localised low Dk pockets in the laminate cause impedance spikes visible on the TDR waveform.
• Copper roughness variation — rougher foil increases effective inductance, nudging impedance up. The effect grows above 10 GHz.

Requesting an Impedance Test Service: Checklist

1. Specify target impedance, tolerance, and the layers that require control in your fabrication notes and stackup drawing.
2. Include coupon artwork in the panel file, or let the fabricator add IPC-2141A coupons—confirm which approach before release.
3. State whether you need a TDR report per lot, per panel, or per board (per lot is standard; per board adds cost).
4. Define the reference plane for each impedance structure (adjacent layer, second-nearest layer, both).
5. Call out any mask-opening or coverlay requirements on the coupons so they mirror the product trace environment.
6. Request the TDR waveform screenshot, not just a pass/fail table—waveforms reveal localised issues a single number hides.

Before submitting Gerbers, take advantage of a free Gerber file review to catch coupon placement and stackup-note errors that would delay the impedance test.

Frequently Asked Questions

What instrument is used for PCB impedance testing?

Most fabricators use a dedicated TDR—commonly the Tektronix DSA8300 or equivalent sampling oscilloscope with a TDR module, or a CITS (Controlled Impedance Test System) from Polar Instruments. Both launch a fast step and measure the reflected waveform to ±0.5 Ω resolution.

How many coupons per panel are typical?

Two to four coupons per panel is standard—one at each end of the panel’s long axis. This catches any impedance gradient caused by etch or press non-uniformity across the panel.

Can TDR test differential impedance directly?

Yes. A differential TDR drives both lines of the pair with equal and opposite steps, measuring Zdiff directly. This is the correct method; computing Zdiff from two single-ended measurements introduces error because it ignores coupling.

Does impedance testing replace VNA S-parameter testing?

No. TDR confirms the trace’s characteristic impedance at DC-equivalent frequencies (roughly DC to the bandwidth set by the pulse rise time). For insertion loss, return loss and frequency-dependent behaviour above a few GHz, a full S-parameter sweep on a vector network analyser is needed.

What IPC standard governs impedance testing?

IPC-2141A (“Design Guide for High-Speed Controlled Impedance Circuit Boards”) covers coupon design and test methodology. IPC-TM-650, Method 2.5.5.7 details the TDR measurement procedure itself. Both are referenced in most controlled-impedance purchase orders.