Impedance Table PCB: Trace Width Reference

What Is an Impedance Table for PCB Design and Why You Need One

An impedance table for PCB design maps the trace width required to hit a target characteristic impedance—typically 50 Ω single-ended or 100 Ω differential—for a specific laminate, copper weight, and dielectric height. Instead of running a field solver from scratch every time, engineers use these impedance table PCB references to sanity-check stackups, compare materials, and catch errors before layout begins. The tables below cover the laminates most commonly specified in RF, microwave, and high-speed digital designs.

Every number in these tables assumes outer-layer microstrip geometry with 1 oz (35 µm / 1.4 mil) finished copper, no solder mask over the trace, and a smooth copper foil (Rz ≤ 2 µm). For stripline or coplanar waveguide geometries, use the microstrip and stripline impedance calculator to adjust.

50 Ω Single-Ended Impedance Table PCB Reference

The table below gives approximate trace widths in both mil (1 mil = 0.0254 mm) and mm for a 50 Ω outer-layer microstrip at several common dielectric thicknesses. Dk values are at roughly 10 GHz unless noted.

Key take-away: lower-Dk laminates need wider traces for the same impedance at the same dielectric height. That is good news for etch tolerance—wider traces are easier to control to ±0.5 mil—but it costs board area. Conversely, high-Dk FR-4 allows narrower traces but makes impedance more sensitive to etch variation. Keeping a reliable impedance table PCB reference on hand lets you spot these trade-offs instantly during early stackup planning.

100 Ω Differential Microstrip Impedance Table

Differential pairs are specified as 100 Ω (Zdiff) in most high-speed protocols (USB 3.x, PCIe Gen 4/5, LVDS) and many RF balanced architectures. The table assumes edge-coupled microstrip with a gap (space) equal to the trace width, which is a common starting point.

Tightening the gap increases coupling and lowers Zdiff; widening it makes each trace behave more like an isolated single-ended line. When your fabricator quotes ±0.5 mil etch tolerance, check how much that shifts Zdiff—at 4 mil trace width, ±0.5 mil is a 12.5 % geometry swing, which can push impedance outside a ±10 % window. This is one reason why controlled impedance PCB fabrication with TDR verification matters.

How to Read and Adapt an Impedance Table PCB Reference

Step 1 — Confirm Your Dk at the Right Frequency

Laminate datasheets usually list Dk at 1 GHz or 10 GHz. FR-4’s Dk drops from about 4.5 at 1 MHz to roughly 4.0–4.2 at 10 GHz. For designs above 6 GHz, always use the 10 GHz value. Rogers publishes frequency-dependent Dk curves in their datasheets; RO4350B process-specific Dk data is a reliable reference.

Step 2 — Know Your Stackup Height

The “dielectric height” in the impedance table PCB columns is the distance from the bottom of the signal trace to the top of the nearest reference plane copper. It is not the total core thickness—pressed prepreg can change the final height by 10–20 % depending on resin content and copper fill. Ask your fabricator for the post-lamination dielectric thickness, not the nominal prepreg callout.

Step 3 — Adjust for Copper Roughness and Solder Mask

Rough copper (standard electrodeposited, Rz ≈ 6–8 µm) increases effective Dk by trapping resin at the interface, which narrows the trace width needed for 50 Ω by 1–2 mil compared to the tables above. Solder mask (Dk ≈ 3.5–4.0) over the trace adds a partial dielectric load that can shift impedance down 2–5 Ω. Both effects must be modeled in a 2-D field solver for production accuracy.

Step 4 — Run a Proper Field Solver

These impedance table PCB values get you within a few percent, but final production widths should come from a calibrated 2-D solver such as Polar Si9000, Altium’s integrated impedance tool, or an equivalent. Plug in the exact Dk, loss tangent, copper profile, and mask parameters your fabricator specifies.

Selecting the Right Laminate for Your Impedance Needs

Choosing a laminate is not just about Dk. Loss tangent (Df), thermal reliability, cost, and availability all factor in. Consult the RF PCB material selection guide for a full decision framework. For a quick side-by-side of Dk, Df, and typical use cases, the RF material cheat sheet is a useful companion.

Nanya Laminates — Mid-Loss FR-4 Alternatives

Nanya produces a range of mid-loss and low-loss FR-4-processable laminates (NP-175F, NP-170D, NP-155F) that sit between commodity FR-4 and high-frequency PTFE in both cost and performance. If your design operates below 6 GHz and standard FR-4’s Df of 0.020 is too high, a Nanya mid-loss grade with Df around 0.008–0.012 may be a cost-effective choice. Use the selector below to match a Nanya laminate to your frequency, Dk, and Tg requirements.

After selecting a Nanya grade, note the Dk value it returns and cross-reference with the 50 Ω impedance table PCB rows above. For example, NP-175F at Dk 4.0 and a 4 mil dielectric height needs roughly 7.3 mil trace width—close to standard FR-4 but with meaningfully lower insertion loss at 2–3 GHz, making it a practical choice for L-band PCB designs.

IPC-4101 Slash Sheet Mapping

When a customer spec or drawing calls out an IPC-4101 slash sheet number (e.g., /126 for high-Tg FR-4, /129 for polyimide), you need to find which commercial laminates qualify. The tool below maps slash sheet numbers to compliant material families so you can then look up the correct Dk for your impedance table.

For instance, IPC-4101/99 covers standard multifunctional FR-4 with Tg ≥ 150 °C. Entering /99 returns laminates with Dk in the 4.2–4.5 range, confirming that the FR-4 rows in the tables above apply directly. If your spec calls out /126 or /128 (high-performance, low-loss), the Dk drops to 3.6–3.9 and you should interpolate between the FR-4 and I-Tera rows.

Common Pitfalls When Using an Impedance Table for PCB Layout

• Using datasheet Dk without specifying frequency. A table built on 1 MHz Dk will over-predict trace width at 10 GHz by 5–10 %.
• Ignoring etch factor. Subtractive etching produces a trapezoidal trace, not a rectangle. The effective width is narrower at the top, which raises impedance. Most field solvers model this; a table cannot.
• Assuming prepreg thickness equals dielectric height. Resin flow into inner-layer copper patterns reduces the actual dielectric gap. Always verify with the fabricator’s controlled-impedance stackup document.
• Copying widths across different copper weights. Going from 1 oz to 0.5 oz copper changes the trace cross-section and shifts impedance by several ohms. Re-solve when copper weight changes.
• Skipping coupon verification. Even with a perfect impedance table PCB reference and solver, process variation means the real board must be checked. Learn how impedance coupons compare to real traces and what discrepancies to expect.

Impedance Table Quick-Reference Checklist

1. Identify your target impedance (50 Ω, 75 Ω, 100 Ω diff, etc.) and geometry (microstrip, stripline, GCPW).
2. Select the laminate and confirm its Dk at your operating frequency.
3. Look up the closest row in the impedance table PCB reference above for a starting trace width.
4. Refine with a 2-D field solver, including copper roughness, solder mask, and etch factor.
5. Send the stackup to your fabricator and request a controlled-impedance build with TDR coupon verification.
6. Compare coupon results to your target; iterate the trace width if outside tolerance.

FAQ

What trace width is needed for 50 Ω on FR-4?

On standard FR-4 (Dk ≈ 4.2) with a 4 mil dielectric height and 1 oz copper, a 50 Ω outer-layer microstrip requires approximately 7.0 mil (0.18 mm) trace width. At 8 mil dielectric height, the width roughly doubles to about 14.5 mil.

Does solder mask change PCB impedance?

Yes. Solder mask with a Dk of 3.5–4.0 partially loads the trace and can lower impedance by 2–5 Ω. Most controlled-impedance builds either account for this in the solver model or specify solder-mask-free windows over critical RF traces.

Can I use the same impedance table for stripline?

No. Stripline is fully embedded between two ground planes, so the effective Dk is higher (no air above the trace) and the required trace width for the same impedance is narrower. Use a stripline-specific solver or table.

How accurate are impedance reference tables?

A well-constructed impedance table for PCB design is typically within ±5 % of a 2-D field solver for standard geometries. Production boards add another ±3–5 % from etch, lamination, and copper roughness variation, which is why TDR coupon verification is standard practice for controlled-impedance builds.

Why does Rogers RO3003 need a wider trace than FR-4 for 50 Ω?

RO3003 has a lower Dk (3.00 vs. 4.2). Lower Dk means the electric field spreads more into air, increasing the characteristic impedance for a given geometry. To bring impedance back down to 50 Ω, you must widen the trace or reduce the dielectric height.