Propagation Delay Calculator | ps per Inch by Dk

What Is Propagation Delay on a PCB?

Propagation delay is the time a signal takes to travel a unit length of PCB trace, typically expressed in picoseconds per inch (ps/in). It depends almost entirely on the effective dielectric constant (Dk_eff) of the substrate surrounding the conductor. For a stripline buried symmetrically between two ground planes, the delay equals roughly 85 × √Dk ps/in. For a microstrip on the surface, where part of the field travels through air, the effective Dk is lower and the delay is shorter.

Knowing the exact delay per inch lets you length-match differential pairs, time high-speed buses, and verify that clock-to-data skew stays within budget—all before the board ships.

The Core Formula

Stripline (fully embedded)

Because all field lines pass through the dielectric:

t_pd = 85.0 × √Dk  (ps/in)

With standard FR-4 at Dk ≈ 4.2, that gives about 174 ps/in (≈ 6.86 ns/m). Switch to Rogers RO4350B (Dk = 3.48) and the delay drops to ≈ 158 ps/in—a 9 % improvement that matters in tight timing margins.

Microstrip (surface trace)

Part of the electromagnetic field travels in air (Dk = 1), so the effective dielectric constant is lower than the bulk Dk. A common first-order approximation is:

Dk_eff ≈ (Dk + 1) / 2 + (Dk − 1) / 2 × (1 + 12 h/w)^−0.5

where h is the dielectric thickness and w is the trace width. The propagation delay then becomes:

t_pd = 85.0 × √Dk_eff  (ps/in)

For a typical 50 Ω microstrip on FR-4 the effective Dk lands near 3.1–3.3, yielding roughly 150–155 ps/in—about 12 % faster than the equivalent stripline on the same laminate.

Interactive Propagation Delay Calculator

Enter your substrate Dk (from the laminate datasheet, at your operating frequency) and trace geometry below. The tool returns propagation delay in ps/in and total delay for a given trace length, for both microstrip and stripline configurations.

A realistic check: on RO4003C (Dk = 3.38 at 10 GHz) with a 10 mil trace over 8 mil dielectric, the calculator should return roughly 148 ps/in for microstrip and 156 ps/in for stripline. If you are routing a 6-inch DDR4 clock trace, that is about 890–940 ps of flight time—well within a single-UI budget at 2400 MT/s but tight enough that a 0.5 inch length mismatch adds ~75 ps of skew, approaching the 100 ps setup window.

Why Dk—and Which Dk—Matters

Laminate vendors publish Dk at multiple frequencies (often 1 MHz, 2.5 GHz, 10 GHz) because Dk drifts downward as frequency rises. Always use the Dk value closest to the knee frequency of your signal, not the 1 MHz number. For a 5 Gbps NRZ signal the knee frequency is about 2.5 GHz; for a 28 Gbps PAM-4 lane it is near 14 GHz. Using the wrong Dk can introduce 5–8 % error in your delay estimate.

The table makes a practical point: moving from FR-4 to RO3003 cuts delay by 15 %. In a phased-array feed network where each element path must be matched to within a few picoseconds, that Dk choice cascades into tighter or looser length-matching tolerances—and directly into manufacturing cost. Consult the Rogers RO4003C datasheet for frequency-dependent Dk curves to anchor your calculation.

Trace Inductance and Its Link to Delay

Propagation delay is fundamentally set by the distributed inductance (L) and capacitance (C) per unit length of the transmission line: t_pd = √(L × C). While Dk dominates the capacitance term, the inductance per unit length depends on trace width, height above the reference plane, and copper thickness. Wider traces lower inductance but raise capacitance; the delay stays nearly constant for a given Dk, which is why Dk is the primary knob.

Still, knowing the inductance per length is essential when you model via transitions or estimate the inductive component of via parasitic inductance. Use the tool below to find the inductance per unit length for your trace geometry.

For a 5 mil wide microstrip on 4 mil FR-4, expect roughly 8–9 nH/in. Pair that with ~3.5 pF/in of distributed capacitance and you get √(8.5 × 3.5) ≈ 5.45 ns/m, consistent with the 174 ps/in stripline figure above when the full Dk is engaged. This cross-check confirms your stackup model is self-consistent before you commit to fabrication.

Practical Design Guidelines

Length Matching for Differential Pairs

The allowable length mismatch is the timing margin divided by the propagation delay. At 156 ps/in on RO4003C with a 25 ps skew budget, the maximum mismatch is 25 / 156 ≈ 0.16 inches (≈ 4 mil). That is aggressive—make sure your EDA tool’s serpentine settings can hit that resolution.

Delay in Antenna Feed Networks

In a microstrip patch array, each feed line must deliver the same electrical delay to maintain beam pointing accuracy. A 1 % Dk variation across the panel shifts delay by about 0.5 %, which at 24 GHz translates to a measurable beam-squint of roughly 0.3° in a 16-element linear array. Specify Dk tolerance of ±0.02 or better for arrays above 10 GHz.

Hybrid Stackups

Many designs mix low-loss RF laminates with FR-4 core layers. Signals crossing from an RO4350B layer (158 ps/in) to an FR-4 layer (174 ps/in) change velocity at the via transition. Account for this when calculating total path delay in multi-layer boards—especially for quarter-wave transformer sections that depend on precise electrical length.

Temperature Effects

FR-4 Dk rises roughly 200 ppm/°C, adding about 0.8 ps/in over a 50 °C swing. PTFE-based laminates are more stable (< 50 ppm/°C). For timing-critical designs operating across wide temperature ranges—automotive radar, for instance—this drift must be budgeted into your skew analysis.

Common Mistakes

• Using 1 MHz Dk for GHz signals. The published “4.5” for FR-4 is a 1 MHz value; at 5 GHz it is closer to 4.0–4.2, depending on resin content.
• Ignoring solder mask. A solder-mask overlay (Dk ≈ 3.3–3.8) raises the effective Dk of a microstrip by 2–5 %, adding 2–7 ps/in. Include it in your model.
• Assuming stripline and microstrip match. A signal routed partly on microstrip and partly on stripline will see a velocity change at each layer transition, creating a small impedance bump and a timing offset.
• Neglecting copper roughness. Rough copper (standard HTE, Rz ≈ 6 µm) increases effective path length and loss, adding ~1–2 % to apparent delay at frequencies above 10 GHz. Specify VLP or HVLP foil for mmWave work.

Tying Delay to System Timing

Propagation delay feeds directly into radar range resolution and antenna scan timing. In an FMCW radar system, the beat frequency depends on round-trip time of flight, and any unaccounted PCB trace delay between the VCO and the antenna adds a fixed range offset. A 100 ps error corresponds to roughly 15 mm of phantom range—negligible for long-range automotive radar but significant in short-range gesture sensors.

For digital buses, the JEDEC DDR4 standard (JESD79-4) specifies data-valid windows that assume controlled propagation delay. Meeting those windows starts with an accurate ps/in number from your actual laminate, at your actual frequency—exactly what the calculator above provides.

Frequently Asked Questions

What is a typical propagation delay for FR-4?

Stripline on mid-grade FR-4 (Dk ≈ 4.2 at a few GHz) gives about 174 ps/in. Microstrip on the same material is roughly 150–155 ps/in because part of the field travels in air, lowering the effective Dk.

Does trace width affect propagation delay?

In stripline, barely—delay is dominated by bulk Dk. In microstrip, wider traces pull more field into the dielectric, raising Dk_eff slightly and increasing delay by 1–3 ps/in compared to a narrow trace on the same stackup.

How do I convert ps/in to ns/m?

Multiply ps/in by 39.37 and divide by 1000. For example, 156 ps/in × 39.37 / 1000 ≈ 6.14 ns/m.

Can I reduce propagation delay without changing the laminate?

Route on a microstrip layer instead of stripline to exploit the lower Dk_eff. You can also widen the trace slightly (lowering Dk_eff by a small amount), but the effect is minor—typically 1–2 %.

Why does solder mask change microstrip delay?

Solder mask (Dk ≈ 3.3–3.8, 1–2 mil thick) sits directly on the trace, replacing some of the air above it with dielectric. This raises Dk_eff and adds roughly 2–7 ps/in, depending on mask thickness and Dk.