Differential Stripline Calculator | Broadside Coupled

What Is a Differential Stripline?

A differential stripline is a pair of conductors embedded between two reference planes inside a PCB stackup, driven with equal-amplitude, opposite-polarity signals. Because both traces are fully shielded by ground planes above and below, differential stripline offers excellent EMI rejection and tightly controlled impedance—making it the preferred routing topology for LVDS, USB 3.x, PCIe Gen 4/5, and RF balanced interconnects above 1 GHz. The two standard coupling arrangements are edge-coupled (traces side by side on the same layer) and broadside-coupled (traces stacked on adjacent layers).

Edge-Coupled vs. Broadside-Coupled Geometry

Choosing between edge-coupled and broadside-coupled stripline affects impedance, coupling, skew and manufacturability. The table below compares the key parameters.

Edge-coupled pairs are far more common in production because they avoid the layer-to-layer registration tolerance that makes broadside pairs harder to control. Broadside coupling is used when very tight coupling (low Zdiff) is needed in a narrow channel, or when the stackup naturally places differential signals on adjacent layers.

Key Parameters for the Differential Stripline Calculator

Inputs you need

• Trace width (W) — typical range 3–8 mil (0.076–0.203 mm) for high-speed digital, wider for lower-frequency RF.
• Trace thickness (T) — finished copper weight; 0.5 oz ≈ 0.7 mil (0.018 mm), 1 oz ≈ 1.4 mil (0.035 mm).
• Trace-to-trace spacing (S) — center-to-center or edge-to-edge gap for edge-coupled; vertical separation for broadside.
• Dielectric height to each reference plane (H1, H2) — distance from trace center to each ground plane.
• Dielectric constant (Dk / εr) — use the value at your operating frequency. For example, Isola I-Tera MT40 has a Dk of 3.45 at 10 GHz, while Rogers RO4350B sits at 3.48 ± 0.05.

Outputs

• Zodd — odd-mode impedance of one trace when driven differentially.
• Zeven — even-mode (common-mode) impedance of one trace.
• Zdiff — differential impedance = 2 × Zodd.
• Zcommon — common-mode impedance = Zeven / 2.

Enter your stackup dimensions below to calculate Zdiff and the odd/even mode impedances for an edge-coupled or broadside-coupled differential stripline pair.

A typical result: with W = 4.5 mil, S = 5 mil gap, H1 = H2 = 10 mil, T = 1.4 mil and Dk = 3.45, you can expect Zdiff near 100 Ω—the standard target for USB 3.x and PCIe. If Zdiff comes back too high, widen the trace or reduce the gap; if too low, narrow the trace or increase the gap. Always verify the result against a 2D field solver in your EDA tool before releasing Gerbers, because the closed-form models the calculator uses carry ±2–5 % uncertainty depending on geometry.

Relating Single-Ended Impedance to Differential

When coupling between the two traces is zero (infinite spacing), Zdiff collapses to exactly 2 × Z0, where Z0 is the single-ended stripline impedance. In practice, coupling always reduces Zodd below Z0, so Zdiff < 2 × Z0. Knowing your single-ended baseline lets you estimate how much coupling your chosen spacing introduces. Use the converter below to move between single-ended and differential impedance quickly.

For example, if your single-ended stripline is 55 Ω and the tool shows Zdiff = 100 Ω, the coupling factor is modest (Zodd ≈ 50 Ω vs. Z0 = 55 Ω). Tighter coupling—useful for better common-mode noise rejection—would push Zodd further below Z0, lowering Zdiff. A 10–15 % reduction from 2 × Z0 is a practical sweet spot that balances noise rejection against fabrication sensitivity.

Stackup Design Rules for Differential Stripline

Symmetric vs. asymmetric strip

A symmetric stripline (H1 = H2) is strongly preferred because it equalizes the field distribution above and below the trace, minimizing mode conversion between differential and common-mode energy. Asymmetric configurations—where the trace sits closer to one reference plane—shift the effective Dk and can degrade return loss at connectors designed for a symmetric field.

Reference-plane continuity

Both ground planes must be continuous copper under the entire differential pair. A split or slot forces return current to detour, creating a common-mode stub that radiates. If you must cross a split, bridge it with stitching vias spaced at λ/20 or closer. You can estimate via parasitics with a via inductance calculator to keep the added impedance below 1 nH.

Dielectric choice and loss

Standard FR-4 (Dk ≈ 4.2–4.5 at 1 GHz, Df ≈ 0.020) works for data rates up to roughly 10 Gb/s per lane. Above that, mid-loss laminates like Megtron 6 (Df ≈ 0.004) or Isola I-Tera MT40 (Df ≈ 0.0031) become necessary. For RF stripline above 10 GHz, PTFE-based materials such as Rogers RO4003C (Dk 3.38, Df 0.0027 at 10 GHz) are common. Copper roughness also matters—use the copper roughness loss model to quantify the extra dB/inch from standard vs. low-profile foil, and consider conductor loss at your frequency to budget total insertion loss.

Common Pitfalls

• Using Dk at 1 MHz for a 10 GHz design. Dk drops with frequency; using the wrong value inflates the calculated trace width and shifts Zdiff by 5–8 %. Always pull Dk from the laminate datasheet at the frequency closest to your signal’s Nyquist rate. Rogers RO4350B datasheet provides Dk at multiple frequencies up to 40 GHz.
• Ignoring etch compensation. Inner-layer traces etch more uniformly than outer layers, but a 0.5 mil over-etch still shifts Zdiff by 3–5 Ω on a 100 Ω target. Ask your fabricator for their typical etch tolerance and add it to your sensitivity analysis.
• Neglecting propagation delay matching. For differential pairs longer than λ/10 at the signal bandwidth, intra-pair skew converts differential energy to common-mode. Use a propagation delay calculator to determine the ps/inch in your dielectric and keep skew under 5 ps for 25+ Gb/s channels.
• Routing differential stripline through via transitions without back-drilling. Stub lengths from unused via barrels create resonant notches. A 40 mil stub resonates near 18 GHz—right inside a 28 Gbps NRZ eye. Back-drill or use blind/buried vias for anything above 10 Gb/s.

Design Checklist

1. Define target Zdiff (e.g., 100 Ω for PCIe, 90 Ω for some LVDS).
2. Select dielectric material and obtain Dk/Df at your Nyquist frequency.
3. Build a symmetric stripline stackup (H1 = H2) with continuous reference planes.
4. Run the differential stripline calculator above to find initial W and S.
5. Verify with a 2D field solver in your EDA layout tool (Cadence Allegro, Altium Designer, KiCad).
6. Add fabrication tolerances (etch, prepreg thickness, Dk lot variation) and confirm Zdiff stays within ±10 % of target per IPC-6012 controlled-impedance requirements.
7. Route pairs with matched lengths; verify intra-pair skew < 5 ps for 25+ Gb/s.
8. Back-drill or use HDI vias to eliminate stubs at layer transitions.

FAQ

What is a typical Zdiff target for differential stripline?

100 Ω is the most common target, used by USB 3.x, PCIe Gen 3–6 and many LVDS interfaces. Some LVDS specifications call for 90 Ω or 120 Ω, so always check the interface standard before designing the stackup.

Can I use FR-4 for differential stripline at 10 GHz?

Standard FR-4 has a dissipation factor (Df) around 0.020 at 1 GHz, which rises further at 10 GHz. Insertion loss becomes prohibitive for traces longer than a few centimeters. Use a low-loss laminate (Df ≤ 0.005) for any stripline carrying energy above roughly 6 GHz.

How does coupling affect common-mode rejection?

Tighter coupling (smaller S or thinner dielectric between broadside traces) increases the difference between Zodd and Zeven, which improves common-mode rejection. However, it also makes Zdiff more sensitive to fabrication tolerances, so there is a practical limit around 15–20 % coupling reduction from the uncoupled baseline.

Edge-coupled or broadside-coupled—which should I choose?

Choose edge-coupled for most designs: it keeps both traces on one layer, avoids layer-to-layer registration error, and is easier to length-match. Choose broadside-coupled only when you need very tight coupling in a narrow channel or when your stackup already places the differential signals on adjacent layers and horizontal space is constrained.

Why does my field solver give a different Zdiff than the calculator?

Closed-form calculators use approximate analytical models that assume ideal geometry and homogeneous dielectric. A 2D field solver meshes the actual cross-section, including trapezoidal etch profiles, solder-mask loading and mixed-Dk prepregs. Expect 2–5 % deviation; always treat the calculator result as a starting point and the field solver as the authority.