5G FR2 mmWave PCB | 28 & 39 GHz Antenna Module Boards

What Is a 5G FR2 mmWave PCB?

A 5G FR2 mmWave PCB is a printed circuit board engineered to carry signals in the 3GPP Frequency Range 2 band—24.25 GHz to 52.6 GHz—with the two most commercially deployed sub-bands centered at 28 GHz (n257/n261) and 39 GHz (n260). These boards combine transmission-line routing, phased-array antenna elements, and power-management structures on a single multilayer substrate, demanding dielectric losses (Df) below 0.004 and trace-width tolerances within ±0.5 mil (0.013 mm). At 28 GHz a quarter-wavelength is roughly 2.7 mm in free space and even shorter in a laminate, so every aspect of the PCB—material, stackup, via transitions, surface finish—directly sets link budget and beam-steering accuracy.

Why FR2 Frequencies Challenge PCB Design

At sub-6 GHz, a typical FR-4 board with a dissipation factor around 0.020 introduces manageable insertion loss. At 28 GHz and above, the same material can lose more than 1 dB per centimeter of microstrip, which is often more than the entire loss budget of a front-end module. Three physics-driven effects dominate:

• Dielectric loss scales with frequency. Loss tangent contributions rise roughly linearly, making low-Df laminates essential.
• Conductor loss rises with the square root of frequency because skin depth shrinks—at 28 GHz skin depth in copper is about 0.39 µm, so surface roughness on the order of 1 µm already degrades performance.
• Radiation and surface-wave losses increase as trace dimensions approach a significant fraction of a wavelength, requiring tighter geometry control and thinner dielectric layers.

These effects together mean that material selection, copper foil type, and fabrication tolerances are not refinements—they are prerequisites for a working 5G FR2 mmWave PCB.

Material Selection for 28 and 39 GHz Boards

High-Frequency Laminates

The table below compares laminates commonly specified for FR2 antenna modules. All values are at 10 GHz per vendor datasheets; actual Dk and Df shift slightly at 28–39 GHz, so designers should request frequency-specific characterization data.

For the antenna layers themselves, PTFE-based materials such as Rogers RO3003 deliver the lowest loss but are difficult to drill cleanly and cannot be processed with standard FR-4 press cycles. Hybrid stackups—PTFE antenna layers bonded to hydrocarbon or low-loss thermoset cores for the digital and power sections—are the mainstream compromise for 5G FR2 mmWave PCB production.

Copper Foil and Surface Roughness

Standard electrodeposited (ED) copper has an Rz roughness of 5–8 µm, which at 28 GHz can add 30–50 % extra conductor loss versus a smooth foil. Reverse-treated (RTF) or very-low-profile (VLP) foils with Rz below 2 µm are preferred. Hyper-VLP foils (Rz ≈ 1 µm) exist but cost roughly 2–3× more and can reduce peel strength, so the trade-off is loss versus lamination reliability.

Stackup Architecture

Typical 28 GHz Antenna Module Stackup

A representative eight-layer stackup for a 28 GHz phased-array module might look like this, from top to bottom:

1. Layer 1 – Patch antenna array: Low-loss PTFE core, 5 mil (0.127 mm) thick, Dk 3.0.
2. Layer 2 – Antenna ground plane: Continuous copper, also serves as the upper reference for the feed network.
3. Layer 3 – Stripline feed network: Hydrocarbon-ceramic core, 4 mil (0.102 mm).
4. Layer 4 – Ground / isolation plane.
5. Layer 5 – RFIC signal routing: Low-loss thermoset, 3.5 mil (0.089 mm).
6. Layer 6 – Power plane.
7. Layer 7 – Digital / control signals: Standard low-loss prepreg.
8. Layer 8 – BGA land pads / thermal relief.

The critical dimension is the dielectric thickness between the patch and its ground (layers 1–2). A ±0.5 mil variation on a 5 mil core shifts the patch resonant frequency by roughly 300–400 MHz at 28 GHz—enough to push the element out of band. Fabricators must hold core thickness to ±0.3 mil or better for FR2 work.

Via Transitions

Every signal via is a discontinuity. At 39 GHz, a standard 10 mil (0.254 mm) drill via with no back-drill can resonate and radiate. Laser-drilled microvias with 4 mil (0.102 mm) capture pads and anti-pad clearances tuned in a 3-D EM solver (HFSS, CST) are standard practice. Back-drilling stubs to within 4 mil of the target layer reduces stub resonance and is mandatory for through-hole transitions that cross more than two layers. Boards targeting mmWave imaging applications at 94 GHz and above face even tighter via constraints, but the same principles apply at FR2 frequencies.

Antenna-in-Package (AiP) and Antenna-on-Board (AoB)

Two integration approaches dominate 5G FR2 mmWave PCB design:

• Antenna-in-Package (AiP): The antenna array is built into the RFIC package substrate (organic or LTCC), and the package is soldered to a host PCB. Qualcomm QTM545 and QTM547 modules follow this path. The host PCB sees only IF or baseband signals plus DC, relaxing its RF requirements.
• Antenna-on-Board (AoB): The antenna elements are etched directly on the system PCB, and the beamformer IC is flip-chip mounted beneath them. This saves package cost and can improve thermal spreading but demands the full low-loss stackup described above across the entire board—or at least across a well-defined RF zone.

Base-station designs (gNodeB active antenna units) lean toward AoB because the board area is large enough to accommodate 64–256 elements with adequate element spacing (roughly 5.4 mm at 28 GHz, half a free-space wavelength). Handset and CPE designs almost universally use AiP because the host PCB is a cost-sensitive multilayer and cannot carry PTFE layers economically. The choice between these architectures is the single biggest decision in a 5G FR2 mmWave PCB program.

Thermal Management

A 256-element active phased array at 28 GHz can dissipate 15–30 W in the beamformer ICs alone. Because mmWave front ends sit at the board edge—close to the antenna aperture—heat must be pulled inward toward heat sinks or chassis. Key techniques include:

• Thermal via arrays: Filled and capped copper vias under each RFIC, on a 1 mm pitch, dropping thermal resistance from junction to backside to roughly 5–8 °C/W per device.
• Embedded copper coins: Press-fit copper slugs in the PCB directly beneath high-power components, providing a continuous metal path with thermal conductivity around 390 W/m·K versus 0.3 W/m·K for the surrounding laminate.
• Thermal interface materials (TIM): Between the coin or via field and an aluminum heat spreader, a TIM with conductivity ≥ 5 W/m·K closes the gap.

Designs for microwave backhaul links in the E-band (71–86 GHz) face similar thermal density challenges, and lessons from those programs transfer directly to FR2 modules.

Manufacturing Tolerances and Process Control

Etching and Line Width

At 28 GHz a 50 Ω microstrip on a 5 mil RO3003 core is roughly 12.5 mil (0.32 mm) wide. A ±1 mil etch tolerance—acceptable at 2 GHz—shifts impedance by about 4 Ω, enough to degrade return loss below 10 dB. Fabricators targeting 5G FR2 mmWave PCB production use modified semi-additive process (mSAP) or laser direct imaging (LDI) to hold line width to ±0.5 mil or better.

Registration and Layer-to-Layer Alignment

A patch antenna fed by a slot in the ground plane needs the slot centered under the patch to within ±1 mil. Misregistration shifts the excitation point, distorting the radiation pattern and increasing cross-polarization. IPC-6012 Class 3 registration requirements are a minimum; many mmWave fabricators work to internal specs tighter than Class 3.

Surface Finish

ENIG (electroless nickel immersion gold) is common but the 3–6 µm nickel layer is ferromagnetic and lossy at mmWave frequencies. ENEPIG replaces some nickel with palladium and is slightly better. For the lowest loss, immersion silver or bare copper with an OSP coat is preferred on antenna layers, with ENIG used only on BGA lands. Some designs use selective surface finish—different chemistries on different areas of the same board—to optimize both solderability and RF performance.

Signal Integrity and Simulation

Full-wave 3-D electromagnetic simulation is non-negotiable for FR2 boards. Every via transition, every bend, every ground-plane slot must be modeled. Typical workflow:

1. Unit-cell simulation: Model one antenna element plus its feed in HFSS or CST; optimize patch dimensions, feed slot, and via fence for the target band (e.g., 27.5–28.35 GHz for n261).
2. Array-level simulation: Expand to a 4×4 or 8×8 sub-array to capture mutual coupling. Element spacing below 0.5 λ₀ raises coupling and scan blindness risk; spacing above 0.6 λ₀ introduces grating lobes.
3. Feed-network co-simulation: Export S-parameters of the antenna array and combine with circuit-level models of the beamformer IC (e.g., Analog Devices ADAR series) in a system simulator to verify EVM, EIRP, and beam-squint across the operating band.
4. Tolerance analysis: Sweep Dk ±3 %, copper roughness ±1 µm, and etch width ±0.5 mil to define the process window. If yield drops below the target, tighten the spec or redesign the element for wider bandwidth.

Phased-array boards for satellite ground terminals in Ka-band (26.5–40 GHz) overlap the FR2 frequency range, and simulation methodologies developed for satcom flat-panel antennas apply directly.

Testing and Qualification

Finished 5G FR2 mmWave PCBs require both electrical and over-the-air (OTA) testing:

• TDR / VNA coupon testing: Impedance coupons on every panel, measured to 40 GHz, verifying controlled impedance within ±5 Ω of target.
• Insertion-loss test coupons: Differential phase-length method per IPC-TM-650 2.5.5.12 adapted for mmWave, targeting total loss under 0.5 dB/cm at 28 GHz on the antenna feed layer.
• OTA pattern measurement: Compact antenna test range or near-field scanner to verify gain, sidelobe level, and beam-steering range of the assembled module.
• Thermal cycling: –40 °C to +85 °C, 500–1000 cycles, checking via integrity and delamination—particularly at the PTFE-to-thermoset bond interface, which is the most common failure point in hybrid stackups.

Design Checklist for 5G FR2 mmWave PCBs

Before releasing Gerbers for a 28 or 39 GHz antenna module board, verify every item below:

• Antenna-layer Dk and Df confirmed at the operating frequency, not just 10 GHz datasheet values.
• Copper foil roughness Rz ≤ 2 µm on all RF layers.
• Core thickness tolerance ≤ ±0.3 mil on antenna dielectric.
• Line-width tolerance ≤ ±0.5 mil on feed-network layers.
• Via stubs back-drilled or eliminated with microvias; stub length < 4 mil.
• Via fences around every transmission line and between antenna elements to suppress surface waves.
• Selective surface finish specified: low-loss finish on antenna, solderable finish on BGA.
• Thermal via field or embedded coin under every beamformer IC.
• Full-wave tolerance sweep completed and process window documented.
• Impedance and insertion-loss coupon designs included on the panel.

Teams working on adjacent mmWave applications—such as 6G research prototype boards above 100 GHz or VSAT flat-panel antenna boards in Ku-band—will find that most items on this checklist scale directly, with tighter numbers at higher frequencies.

Frequently Asked Questions

Can FR-4 be used for a 5G FR2 mmWave PCB?

Not for the antenna or RF feed layers. Standard FR-4 has a Df of 0.018–0.025 at 10 GHz, which translates to roughly 2–3 dB/cm insertion loss at 28 GHz—far too high for a functional link. FR-4 can be used for digital and power layers in a hybrid stackup, but the RF-critical layers must use a low-loss laminate with Df below 0.004.

What is the typical layer count for a 5G FR2 antenna module?

Six to ten layers is common. A minimal AoB design might use six layers (patch, ground, feed, ground, signal, ground), while a fully integrated module with embedded power regulation and digital control can reach ten or twelve layers.

How does 39 GHz design differ from 28 GHz?

At 39 GHz, the half-wavelength element spacing drops to about 3.8 mm, tightening routing density. Conductor and dielectric losses are both higher, so maximum trace lengths shrink. Dielectric thickness tolerances that are acceptable at 28 GHz may need to be halved at 39 GHz. The same materials work, but process windows narrow significantly.

What is the role of via fencing in mmWave PCBs?

Via fences—rows of grounded vias spaced at less than λ/10 (about 1 mm at 28 GHz)—act as a pseudo-waveguide wall. They suppress parallel-plate modes between ground planes, reduce crosstalk between adjacent channels, and prevent surface-wave coupling that degrades antenna sidelobe levels. Omitting via fences is one of the most common first-time design errors in FR2 boards.

Is antenna-in-package or antenna-on-board better for 5G FR2?

AiP is better when the host PCB must remain low-cost (handsets, CPE) or when the RFIC vendor provides a validated module. AoB is better for base stations and custom arrays where thermal management, element count, and aperture size favor direct PCB integration. Neither is universally superior; the choice depends on volume, thermal budget, and system architecture.