6G PCB Design | Sub-THz 100 GHz+ Prototype Boards

What Is a 6G PCB and Why Does It Matter?

A 6G PCB is a printed circuit board engineered to operate in the sub-terahertz bands—roughly 100 GHz to 300 GHz—that sixth-generation wireless research targets for peak data rates beyond 100 Gbit/s. At these frequencies a free-space wavelength of 1–3 mm shrinks critical PCB features into the tens-of-microns range, making substrate loss, copper roughness, and via transition quality the dominant performance limiters. Every design choice that was “good enough” at 28 GHz or 77 GHz must be revisited for 6G.

Research groups worldwide—at universities, national labs, and semiconductor houses—are already prototyping 6G front-end modules on PCB and package substrates. The boards serve as evaluation platforms for D-band (110–170 GHz) and G-band (140–220 GHz) transceiver ICs, phased-array feed networks, and integrated antenna arrays. Understanding the PCB constraints now is essential for anyone who will design, specify, or procure these boards as 6G standards solidify toward the projected 2030 deployment window.

Frequency Bands Driving 6G PCB Requirements

While 6G research spans many candidate bands, three clusters create the most immediate PCB design pressure:

At 140 GHz, a quarter-wavelength microstrip stub is only about 270 µm long on a substrate with a Dk of 3.0. Fabrication tolerances that cause a ±5 % length error at 28 GHz produce a ±25 % error at 140 GHz relative to the wavelength, making dimensional control the single biggest yield risk on a 6G PCB. For deeper discussion of boards operating above 100 GHz, see our guide to terahertz PCB substrates and interconnects.

Substrate Materials for Sub-THz Operation

Why Conventional Laminates Fail Above 100 GHz

Standard RF laminates such as Rogers RO4350B (Dk 3.48, Df 0.0037 at 10 GHz) perform well through Ka-band, but their dissipation factor rises with frequency. By 100 GHz, even premium hydrocarbon-ceramic blends can exhibit Df values of 0.006–0.008, translating to conductor-plus-dielectric losses above 2 dB/cm for a 50 Ω microstrip. For a 6G front-end where the entire signal path from IC pad to antenna element may be only 5–10 mm, that loss budget is already consumed.

Materials That Work

Sub-THz prototype boards overwhelmingly use one of four material families:

• Liquid crystal polymer (LCP): Dk ≈ 2.9, Df ≈ 0.002 at 100 GHz. Thin films (25–100 µm) enable low-loss stripline and embedded antenna structures. Multilayer LCP laminates are bondable without adhesive layers, avoiding extra loss interfaces.
• Modified PTFE composites: Rogers RT/duroid 5880 (Dk 2.20, Df 0.0009 at 10 GHz) remains attractive, though its softness complicates fine-line etching. Variants filled with ceramic microspheres improve dimensional stability.
• Low-temperature co-fired ceramic (LTCC): Dk ≈ 5.7–7.8 depending on tape system. High Dk shrinks wavelength further (a challenge), but LTCC offers hermetic packaging and embedded cavities for IC integration.
• Fused silica / quartz: Dk ≈ 3.8, Df < 0.0004 at 140 GHz. Extremely low loss, but requires thin-film metallization and cannot be processed on standard PCB equipment.

Rogers Corporation publishes measured Dk/Df data up to 77 GHz for many grades in its RO4350B product data sheet; extrapolation above that range should be validated with split-cylinder or Fabry–Pérot resonator measurements on the actual production lot.

Stackup Architecture for 6G PCBs

Thin-Core Stripline vs. Substrate-Integrated Waveguide

Two transmission-line topologies dominate 6G prototype boards:

• Thin-core stripline: A signal trace buried between two ground planes separated by 50–100 µm of LCP or PTFE. Stripline confines fields fully inside the dielectric, eliminating radiation loss that becomes severe on open microstrip above 100 GHz. The penalty is tighter via clearance requirements and the need for laser-drilled microvias with diameters of 50–75 µm.
• Substrate-integrated waveguide (SIW): Two rows of plated vias form the sidewalls of a waveguide channel within the PCB. At D-band the via pitch must be under 300 µm (≈ λ/5 in the dielectric) to suppress leakage. SIW offers lower loss than microstrip at the cost of larger footprint and more complex transitions to IC pads.

Hybrid stackups are common: SIW for feed distribution, transitioning through a slot or probe to a thin-core stripline that connects to a flip-chip MMIC. The transition geometry is typically optimized in a full-wave solver (HFSS, CST) with fabrication tolerances included as Monte Carlo variables.

Layer Count and Symmetry

Most D-band prototypes use 4–8 layers. Maintaining symmetry around the core is critical because even 5 µm of dielectric-thickness asymmetry between the upper and lower ground planes of a stripline shifts the characteristic impedance by several ohms at 140 GHz. Specifying a lamination tolerance of ±5 µm—rather than the ±25 µm common in commercial multilayer PCBs—is realistic only with vacuum-press lamination and post-etch dielectric-thickness verification.

Copper Roughness and Skin Effect

At 140 GHz the skin depth in copper is approximately 0.18 µm. Surface roughness on standard electrodeposited (ED) copper foil (Rz ≈ 5–8 µm) is 30–40× the skin depth, creating a tortuous current path that can double the effective conductor loss compared to a smooth surface. The Hammerstad–Jensen roughness correction factor, commonly used at lower frequencies, underestimates this effect above 60 GHz; the Huray snowball model or full-wave surface-impedance extraction is more accurate.

Practical mitigation strategies:

• Rolled-annealed (RA) copper with Rz < 1.0 µm, bonded to LCP with plasma surface activation instead of mechanical roughening.
• Sputtered or evaporated thin-film metallization (Ti/Cu/Au) on quartz or LCP, achieving Rz < 0.1 µm. This is standard in MMIC processing but unusual in PCB shops; a few specialty fabricators offer it on panel sizes up to 150 × 150 mm.
• Reverse-treated foil (RTF) grades such as those specified in IPC-4562 revision B, which classifies foil roughness profiles and helps designers specify the grade needed for a target frequency.

Interconnect and Transition Challenges

Flip-Chip and Wire-Bond Parasitics

A 25 µm gold bond wire presents roughly 0.7–1.0 nH of series inductance, which at 140 GHz is an impedance of over 600 Ω—effectively an open circuit. Flip-chip attachment with solder bumps (75–100 µm pitch) or gold stud bumps (50 µm) is therefore mandatory for 6G MMICs. The bump itself contributes capacitance and a short transmission-line section; co-design of the bump geometry with the PCB pad and anti-pad is essential.

Via Transitions

Signal vias that connect layers in a 6G PCB act as resonant stubs if their length and anti-pad diameter are not carefully controlled. Blind microvias drilled by UV or CO₂ laser, with diameters of 50–75 µm and aspect ratios of 1:1, minimize stub length. Back-drilling—common at 28 GHz to remove via stubs—is too imprecise for D-band work because the mechanical drill tolerance (±50 µm) is a significant fraction of a wavelength. Controlled-depth laser ablation is the preferred stub-removal technique.

These interconnect concerns overlap with those faced in 60 GHz radar PCB design, but at 6G frequencies the tolerances tighten by roughly another factor of two.

Antenna Integration on 6G PCBs

At D-band, a half-wavelength patch antenna element is approximately 0.7 mm wide on an LCP substrate (Dk ≈ 2.9). Arrays of 64–256 elements fit within a 15 × 15 mm aperture, making PCB-integrated phased arrays practical. Key design considerations include:

• Element spacing: λ₀/2 at 140 GHz is about 1.07 mm, setting the array lattice. Tighter spacing suppresses grating lobes for wide scan angles but increases mutual coupling.
• Feed network loss: Corporate feed networks using SIW or stripline must keep total distribution loss under 3–4 dB to preserve effective isotropic radiated power (EIRP). Series-fed linear sub-arrays reduce path length but narrow the instantaneous bandwidth.
• Surface-wave suppression: Thick substrates relative to wavelength launch surface waves that degrade pattern and increase scan blindness risk. Keeping substrate thickness below λ₀/(4√ε_r) is a common guideline; for LCP at 140 GHz, that limit is roughly 160 µm.

Antenna-in-package (AiP) approaches, where the antenna array is built on the IC package substrate rather than the system PCB, are a competing architecture. However, PCB-level integration offers a larger aperture and easier thermal management for high-EIRP links, which is why many 6G research demonstrators still use PCB antennas. Groups working on defense-oriented wideband systems face similar array integration challenges on electronic warfare PCBs.

Fabrication Tolerances and Process Requirements

These tolerances push fabrication out of mainstream PCB production and into the overlap zone between advanced HDI PCB shops and semiconductor packaging foundries. Expect lead times of 6–12 weeks for first-article prototypes and per-board costs that are an order of magnitude higher than equivalent 5G mmWave panels.

Testing and Characterization

Verifying a 6G PCB requires instrumentation that most board houses do not own. Key test setups include:

• Vector network analysis to 220 GHz or 330 GHz using frequency-extension modules (e.g., WR-6.5 or WR-3.4 waveguide bands) with on-wafer or on-board GSG probes at 100–150 µm pitch.
• Near-field antenna scanning at D-band with sub-millimeter spatial resolution to verify array patterns and identify element failures.
• Time-domain reflectometry (TDR) with a rise time below 10 ps, needed to resolve impedance discontinuities shorter than 0.3 mm.

Calibration substrate quality matters enormously: an imperfect TRL calibration kit fabricated on the same laminate lot as the DUT is usually more accurate than a commercial ISS calibration substrate designed for a different Dk.

Thermal Management at Sub-THz Power Levels

Current D-band power amplifiers deliver only 10–100 mW of saturated output power per MMIC, but they do so at 5–15 % power-added efficiency, meaning 0.5–2 W of heat in a die smaller than 2 × 2 mm. LCP and PTFE are poor thermal conductors (0.2–0.3 W/m·K), so thermal vias under the MMIC—arrays of filled copper vias on a 200 µm pitch connecting to a ground plane backed by a metal carrier—are essential. Some research groups embed copper coin inserts or use aluminum-nitride (AlN) interposers between the MMIC and the organic PCB to bridge the thermal-conductivity gap.

Thermal challenges at this scale share design philosophy with space-qualified boards used in CubeSat RF transceiver modules, where limited heat-sinking area also demands creative via-based thermal paths.

Design Workflow and EDA Considerations

A practical 6G PCB design flow typically proceeds as follows:

1. System link budget: Establish required EIRP, noise figure, and channel bandwidth to determine array size and acceptable PCB loss.
2. Substrate selection: Choose material and thickness based on loss, processability, and MMIC attachment method.
3. Full-wave simulation: Model every transition (IC-to-board, via, stripline-to-SIW, SIW-to-antenna) in a 3-D electromagnetic solver with measured Dk/Df and roughness parameters. Parametric sweeps over fabrication tolerances are not optional—they are the only way to predict yield.
4. Layout with DFM checks: Coordinate with the fabricator early; many features (50 µm vias, ±5 µm trace tolerance) require process-specific design rules that differ from the fabricator’s standard capability tables.
5. First-article test: Measure S-parameters, radiation patterns, and impedance before committing to a panel run.

Frequently Asked Questions

Can FR-4 be used for any part of a 6G PCB?

FR-4 can serve as a structural carrier or low-frequency power-distribution layer in a hybrid stackup, but it must never carry sub-THz signals. Its Df of 0.020+ at 10 GHz makes it unusable above a few gigahertz for signal traces.

What is the lowest-loss PCB material at 140 GHz?

Fused silica (quartz) with thin-film metallization offers the lowest combined conductor-plus-dielectric loss, typically below 0.5 dB/cm at 140 GHz. Among organic laminates, LCP is the current leader at roughly 0.8–1.2 dB/cm depending on thickness and copper treatment.

How does 6G PCB design differ from 5G mmWave?

The primary differences are a 3–5× tightening of all dimensional tolerances, mandatory use of ultra-low-roughness copper, a shift from microstrip to enclosed transmission lines (stripline or SIW), and the need for flip-chip rather than wire-bond IC attachment.

Are 6G PCBs commercially available today?

No standard commercial 6G PCBs exist because 6G standards are still in the research phase (ITU-R IMT-2030 framework). What is available are custom prototype boards from specialty fabricators experienced in D-band and G-band work, typically at research-lab quantities of 5–20 boards per order.

What role does substrate-integrated waveguide play in 6G boards?

SIW provides a shielded, low-radiation-loss transmission medium within the PCB stackup. At D-band it can achieve insertion loss below 0.3 dB/cm—roughly half that of microstrip on the same substrate—making it the preferred feed-network topology for high-element-count phased arrays.