Etch Compensation RF PCB: Trace Width Guide

What Is Etch Compensation on an RF PCB?

Etch compensation is the deliberate widening of trace artwork to offset the copper that chemical etching removes from the sides of a conductor. Because etchant attacks copper isotropically—top, bottom, and sideways—the finished trace is always narrower at the top than at the base, forming a trapezoid rather than the ideal rectangle drawn in CAD. On an RF PCB, where a 50 Ω microstrip may be only 12 mil (0.30 mm) wide, even 1 mil of uncompensated side-etch can push impedance 2–5 Ω above target and degrade return loss across an entire band. Mastering etch compensation RF PCB techniques is one of the most cost-effective ways to hit tight impedance windows.

Getting the compensation right matters more here than on digital boards because RF structures operate at frequencies where small geometry errors translate directly into measurable mismatch. The rest of this article explains the mechanism, gives you the numbers, and lets you calculate the compensation for your own stackup. For background on achievable tolerances, see RF PCB tolerance capabilities.

Why Etching Creates a Trapezoid

Subtractive etching starts with a copper-clad laminate, applies photo-resist to protect the trace pattern, and dissolves the exposed copper in an acidic or alkaline solution. The etchant reaches the copper surface first, so the top of the trace is exposed to chemistry longer than the base, which is shielded by the resist above. The result is an undercut beneath the resist edge on each side.

Etch Factor and Undercut

The etch factor (EF) is the ratio of copper thickness etched downward to the lateral undercut on one side:

EF = copper thickness / undercut per side

A typical alkaline-etch line achieves an etch factor of 2.5–3.5 for ½ oz (17 µm) copper, dropping to 2.0–2.5 for 1 oz (35 µm) and as low as 1.5–2.0 for 2 oz (70 µm). Acidic cupric chloride processes can reach EF 3.0–4.0 on thin copper. The higher the etch factor, the more vertical the sidewall and the less compensation you need.

Trapezoid Geometry

After etching, the trace cross-section has a top width W_top and a bottom width W_bot. The undercut per side (U) relates them:

W_bot = W_top + 2 × U

For impedance modeling, many field solvers use the average width:

W_avg = (W_top + W_bot) / 2

Impedance depends primarily on this average width, the dielectric constant (Dk), dielectric height, and copper thickness. A 2D field solver such as those used in an impedance modeling service can model the actual trapezoid, which is more accurate than using W_avg alone—especially for thick copper or very narrow lines.

How Etch Compensation RF PCB Artwork Is Adjusted

The designer or fabricator adds extra width to the artwork so the finished (post-etch) trace hits the target dimension. The compensation amount per side equals the expected undercut:

Artwork width = target finished width + 2 × (copper thickness / EF)

For example, a 50 Ω microstrip on RO4350B (Dk 3.48, 6.6 mil dielectric) needs a finished W_avg of about 14.3 mil on 1 oz copper. If the shop’s etch factor is 3.0, the undercut per side is 35 µm / 3.0 ≈ 12 µm (0.47 mil), so the artwork trace should be 14.3 + 2 × 0.47 ≈ 15.2 mil. Without that correction, the finished trace would be roughly 13.4 mil and impedance would rise to about 53–54 Ω.

Who Applies the Compensation?

This depends on the fabrication workflow:

• Fabricator-applied (most common): The designer supplies artwork at the target finished width. The fabricator’s CAM department adds etch compensation based on their process data. This is the safest approach because the shop knows its own etch factor.
• Designer-applied: Sometimes required when the designer controls the Gerber files tightly or uses a Gerber, ODB++, or IPC-2581 export with pre-compensated widths. In this case, the fabrication note must state that artwork is already compensated.

Misunderstanding who owns the compensation is a leading cause of first-article impedance failures. Always state it explicitly in the fabrication drawing.

Copper Weight, Thickness, and Etch Compensation RF PCB Table

Heavier copper demands more compensation because the etchant must dissolve more metal vertically, giving it more time to undercut laterally. The table below shows typical numbers for alkaline etching on inner layers.

Use the calculator below to see how copper weight and etch factor interact for your specific design. Enter your target finished trace width, copper weight, and the etch factor your fabricator quotes. The tool returns the artwork width you need and the resulting trapezoid dimensions.

As a quick sanity check: if you entered 1 oz copper with an etch factor of 3.0 and a target finished width of 10 mil, the calculator should return an artwork width near 10.9 mil, with a top width of about 10 mil and a bottom width near 11.9 mil. That 1.9 mil difference between top and bottom is the trapezoid effect that your impedance model must account for. If you are designing a mixed dielectric stackup with different copper weights on different layers, run the calculation separately for each layer.

Impedance Impact of the Trapezoid Profile

How Much Does Impedance Shift?

A useful rule of thumb for 50 Ω microstrip on common RF laminates: every 1 mil of trace width change shifts impedance roughly 2–4 Ω, depending on dielectric height and Dk. The trapezoid effect narrows the top of the trace relative to the base, so the effective width is less than the artwork width. If the impedance model assumes a rectangular cross-section at the artwork width, it will predict impedance lower than reality. Conversely, modeling at the top width alone overshoots impedance.

Modeling Best Practices

• Use a trapezoidal cross-section in your field solver. Altium’s impedance-driven design tools and Polar Si9000 both support trapezoid geometry natively.
• Specify the etch factor, not just the finished width. The solver needs both W_top and W_bot; supply them or let the solver derive them from EF and copper thickness.
• Request coupon data from the fabricator. First-article impedance coupons measured with a TDR reveal the actual etch factor achieved, which may differ from the quoted nominal. Per IPC-6012 Class 3, impedance must be within ±10 % for standard RF work, but many radar and satcom designs tighten this to ±5 %.

Etch Compensation RF PCB Structures: Microstrip, Stripline, CPWG

Microstrip

Microstrip is the most sensitive to etch variation because the trace sits on the surface, exposed to the etchant from three sides (top is resist-protected). Compensation values are straightforward: use the formula above. On PTFE laminates, the copper-to-substrate adhesion profile can slightly alter the undercut at the base; work with a fabricator experienced in bonded multilayer PTFE builds.

Stripline

Inner-layer stripline traces are etched on a copper-clad core before lamination. The etch factor on inner layers is generally more consistent than on outer layers because the process is simpler (no plating resist step). However, stripline impedance is more sensitive to dielectric thickness tolerance than to trace width, so etch compensation alone does not guarantee a good result—press-out thickness control matters equally.

Coplanar Waveguide (CPWG)

CPWG impedance depends on both the signal trace width and the gap to the coplanar ground. Etch compensation must be applied symmetrically: the signal trace gets wider and the gap gets narrower by the same undercut amount. Failing to compensate the gap is a common oversight that shifts impedance in the opposite direction from what the trace compensation alone would suggest.

Edge-Coupled Differential Pairs

Differential pairs are doubly sensitive: both trace width and the coupling gap change with etch. The coupling gap widens by twice the undercut (one undercut from each trace facing the gap), weakening coupling and raising differential impedance. Artwork compensation must widen each trace and narrow the gap simultaneously. Designs with tight coupling gaps below 4 mil on 1 oz copper are particularly risky—consider moving to ½ oz copper to reduce the undercut.

Process Variables That Affect Etch Factor

Etch factor is not a fixed constant; it varies with:

• Etchant chemistry: Cupric chloride gives tighter sidewalls than ammoniacal alkaline etch for the same copper thickness.
• Conveyor speed and spray pressure: Higher pressure pushes fresh etchant into the undercut zone, which can increase lateral etch.
• Copper type: Electrodeposited (ED) copper etches more uniformly than rolled-annealed (RA) copper due to grain structure differences.
• Resist type and adhesion: Dry-film resist with strong adhesion limits etchant wicking under the resist edge, improving EF.
• Panel position: Traces near panel edges may see different spray dynamics than those at center, causing EF variation across the panel. Good RF panel utilization planning can mitigate this by keeping critical traces away from panel borders.

Practical Guidelines and Checklist

1. State the impedance target, tolerance, and copper weight on the fab drawing. Let the fabricator own etch compensation unless you have a specific reason not to.
2. Use ½ oz copper for fine-line RF traces (< 6 mil). The undercut is roughly half that of 1 oz, making impedance control far easier.
3. Model the trapezoid, not a rectangle. Ask your fabricator for their typical etch factor per copper weight and feed it into the field solver.
4. Request impedance coupons on every panel. TDR-measured coupons are the only reliable verification that compensation was correct.
5. Watch the gap, not just the trace. For CPWG and differential pairs, gap compensation is as important as trace compensation.
6. Re-qualify etch factor when changing fabricators or copper suppliers. A new shop’s EF may differ by 0.5 or more, shifting impedance outside your window.
7. For prototypes, build impedance test vehicles first. A quick-turn RF PCB prototype run with coupons lets you lock in the etch factor before committing to a production lot.

When Etch Compensation RF PCB Methods Are Not Enough

At millimeter-wave frequencies (above ~30 GHz), the trapezoid profile itself becomes an electromagnetic concern—not just the average width. The sloped sidewalls change the current distribution and increase conductor loss compared to vertical walls. For 77 GHz automotive-grade radar PCBs, some designers specify semi-additive (mSAP) or laser-direct-imaging (LDI) processes that produce near-vertical sidewalls with etch factors above 5, reducing the need for heavy compensation. These processes cost more but may be the only way to hold ±3 % impedance on sub-4-mil traces at millimeter-wave frequencies where sidewall geometry matters.

FAQ

How much etch compensation do I need for 1 oz copper on an RF PCB?

For 1 oz (35 µm) copper with a typical alkaline etch factor of 2.5–3.0, expect to add approximately 0.9–1.1 mil (23–28 µm) total to the artwork width—roughly 0.5 mil per side.

Should the designer or fabricator apply etch compensation?

In most etch compensation RF PCB workflows, the fabricator applies it during CAM processing because they know their actual etch factor. If you pre-compensate, clearly note it on the fab drawing to avoid double compensation.

Does etch compensation change with frequency?

The physical etch process is frequency-independent. However, at higher frequencies the electrical impact of the trapezoid profile is more significant, so accurate compensation and modeling become more critical above 10 GHz.

Can I avoid the trapezoid effect entirely?

Semi-additive processes (mSAP) build traces by plating rather than etching, producing nearly rectangular cross-sections. This eliminates most undercut but increases cost and is typically reserved for mmWave designs above 40 GHz.

How does plating affect etch compensation on outer layers?

Outer-layer traces receive additional copper during through-hole plating, typically 20–25 µm. This extra thickness must be included when calculating undercut. The total copper to etch is the base foil plus the plated copper, so outer-layer compensation is usually larger than inner-layer compensation for the same starting foil weight.