RT Duroid 5870 PCB Design & Fabrication Guide

What Is an RT Duroid 5870 PCB?

An RT Duroid 5870 PCB is a printed circuit board built on Rogers Corporation’s glass-microfiber-reinforced PTFE laminate, which offers a dielectric constant (Dk) of 2.33 ± 0.02 at 10 GHz and a dissipation factor (Df) of 0.0012. Its exceptionally low loss and tightly controlled Dk make the RT Duroid 5870 PCB a first-choice substrate for microwave stripline and microstrip circuits from 1 GHz through 40 GHz, including satellite communications feed networks, radar front-ends, and millimeter-wave antenna arrays.

The material’s random glass-microfiber reinforcement—rather than a woven-glass weave—gives it an unusually isotropic Dk in the x-y plane, which matters whenever a circuit carries signals at multiple orientations such as in circular-polarization patch antennas. Compared with woven-glass PTFE laminates like glass-reinforced PTFE substrates, the microfiber construction eliminates the periodic Dk modulation (“fiber-weave effect”) that can create phase skew in wide transmission lines.

Key Material Properties of RT Duroid 5870

Two numbers stand out. First, the Df of 0.0012 is among the lowest available in any rigid PCB laminate; this translates directly into lower insertion loss per unit length, which is critical for long feed-line runs in phased-array antennas. Second, the moisture absorption of 0.02 % means the Dk stays stable in humid environments—an important consideration for outdoor radar and satcom hardware.

Where RT Duroid 5870 PCBs Are Used

Satellite and Space Communications

Feed networks for C-band through Ka-band satellite antennas rely on RT Duroid 5870 PCB technology because its low Dk yields wider microstrip traces for a given impedance, reducing conductor loss. The material is also qualified for space environments thanks to its low outgassing and negligible moisture uptake.

Radar Systems

Marine navigation radar, weather radar, and military fire-control radar at X-band (8–12 GHz) and Ku-band (12–18 GHz) commonly use 5870 for corporate feed networks and Butler matrices. For higher-Dk radar applications—such as miniaturized patch elements—designers often pair 5870 feed layers with a higher-Dk laminate like RT/duroid 6010LM (Dk 10.2) for the radiating layer.

Millimeter-Wave Test Fixtures

Because the Dk tolerance is ±0.02 (less than 1 %), 5870 is popular for calibration substrates and test fixtures where repeatable impedance is non-negotiable.

Low-Noise Amplifier (LNA) Boards

The low Df minimizes substrate-related noise, making 5870 a natural fit for LNA front-end boards in radio astronomy and sensitive receiver chains.

RT Duroid 5870 PCB vs. Similar Low-Dk Laminates

Choose an RT Duroid 5870 PCB when you need a Dk of 2.33 with isotropic in-plane behavior and ultra-low loss—typical of wideband microstrip feed networks. Choose RT/duroid 5880LZ (Dk 1.96) if you need the absolute lowest Dk for the widest possible trace widths or lowest phase velocity. Choose CuClad 233 when you want the same Dk 2.33 but need better dimensional stability from woven-glass reinforcement and can tolerate minor fiber-weave effects. Choose Taconic TLY-5 when ultimate loss performance matters more than mechanical rigidity.

Stackup Design for RT Duroid 5870 PCBs

Most RT Duroid 5870 PCB designs are single- or double-sided, but multilayer stackups of 4–6 layers are achievable by bonding cores with Rogers 3001 bonding film (PTFE-based, Dk 2.28) or with RT/duroid 6202PR prepreg. The bonding film keeps the overall Dk uniform, avoiding the Dk mismatch that would result from using FR-4 prepreg between PTFE cores.

Typical 4-Layer Stackup

• Layer 1 (Signal): Microstrip on 10 mil (0.254 mm) RT/duroid 5870 core
• Layer 2 (Ground): Copper plane
• Bonding layer: Rogers 3001 bonding film, 1.5 mil (0.038 mm)
• Layer 3 (Ground / Power): Copper plane
• Layer 4 (Signal): Microstrip on 10 mil RT/duroid 5870 core

Use the stackup designer below to model your own layer arrangement and verify total board thickness, impedance references, and bonding-layer placement.

A realistic result for the 4-layer RT Duroid 5870 PCB stackup above would yield a total board thickness of roughly 23.5 mil (0.60 mm) excluding plating, with each microstrip signal layer referenced to the adjacent ground plane through 10 mil of Dk 2.33 dielectric. At 10 GHz, a 50 Ω microstrip on this 10 mil core calculates to approximately 25.4 mil (0.645 mm) wide—comfortable to etch with standard photolithography. If the tool returns a trace width narrower than 4 mil (0.10 mm) for your target impedance, consider moving to a thicker core or reducing the impedance target, because PTFE’s softness makes very narrow traces mechanically fragile during handling.

Fabrication Process Considerations

Copper Adhesion and Surface Preparation

PTFE is chemically inert, which means copper does not bond well to bare PTFE surfaces. RT/duroid 5870 panels ship with electrodeposited (ED) copper that has been factory-treated for adhesion. If you need to re-bond copper or add a bonding film, a sodium-naphthalene etch (chemical surface treatment) or plasma treatment is required to activate the PTFE surface. Peel strength after proper treatment exceeds 26 N/cm; without it, delamination under thermal cycling is almost certain.

Drilling

PTFE laminates are soft and “gummy,” so standard FR-4 drill parameters cause smearing and ragged hole walls. Best practices:

• Use carbide drill bits with high positive rake angles (30°–35°).
• Reduce infeed rate to 0.025–0.05 mm/rev to avoid tearing the PTFE matrix.
• Back up with a rigid entry/exit material (aluminum sheet) to prevent burring.
• For vias smaller than 0.3 mm (12 mil), laser drilling or controlled-depth mechanical drilling yields cleaner results.

Plating and Via Metallization

The PTFE hole wall is non-wettable, so direct electroless copper deposition often fails. A sodium-etch or plasma desmear step is mandatory before the electroless copper seed. Many fabricators use a dedicated “PTFE via preparation” line rather than their standard desmear cycle. Skipping this step is the single most common cause of via reliability failure in PTFE boards. IPC-6012 rigid board qualification Class 3 requires minimum 25 µm (1 mil) copper in plated through-holes; achieving this on PTFE demands careful control of the seed layer.

Etching

Standard alkaline or cupric-chloride etch chemistries work fine on RT/duroid 5870 copper. Because the substrate is soft, use vacuum hold-down on the conveyor to prevent panel warpage. Etch-factor control matters more here than on rigid substrates: the wide traces typical of low-Dk designs are forgiving, but coupled-line filters with tight gaps (< 5 mil) require tightly controlled etch chemistry and photoresist adhesion.

Solder Mask and Surface Finish

Liquid photoimageable (LPI) solder mask adheres poorly to PTFE. Options include:

• Coverlay film: A polyimide or PTFE film bonded over non-signal areas.
• Selective solder mask: Apply LPI only over FR-4 or polyimide stiffener regions in hybrid boards.
• No mask: Many pure-PTFE microwave boards ship without solder mask, relying on conformal coating or housing shielding instead.

For surface finish, electroless nickel/immersion gold (ENIG) and immersion silver are the most common choices. ENIG adds roughly 3–5 µm of nickel, which can increase conductor loss at frequencies above 20 GHz due to the skin effect; immersion silver avoids this but has a shorter shelf life.

Design Rules and Trace Geometry

Microstrip Line Width

For a 50 Ω microstrip on an RT Duroid 5870 PCB (Dk 2.33), the approximate width-to-height ratio (W/h) is about 3.1. On a 10 mil core, that gives a trace width near 31 mil (0.79 mm); on a 20 mil core, roughly 62 mil (1.57 mm). These are comfortably wide traces, which is one of the practical advantages of a low-Dk substrate—wider copper means lower ohmic loss.

Coupled Lines and Filters

Edge-coupled microstrip filters on 5870 require wider gaps than on higher-Dk materials for the same coupling coefficient, because the fringing fields extend further in a low-Dk medium. Plan for minimum gaps of 4–5 mil (0.10–0.13 mm) for production reliability, and simulate coupling with a 2.5-D field solver rather than relying on closed-form equations.

Via Transitions

Signal vias through PTFE stackups introduce parasitic inductance and capacitance. At frequencies above 20 GHz, use back-drilled or blind vias to minimize the stub length. A via stub of 20 mil in a Dk 2.33 medium resonates near 74 GHz—generally safe for Ku-band designs but problematic if the board is reused at Ka-band without back-drilling.

Thermal and Mechanical Considerations

RT/duroid 5870’s z-axis CTE of 237 ppm/°C is high compared with FR-4 (~60 ppm/°C) or ceramic-filled PTFE like RT/duroid 6002 (24 ppm/°C z-axis). This means plated through-holes in an RT Duroid 5870 PCB experience significant barrel stress during thermal excursions. For boards that will see repeated –55 °C to +125 °C cycling (military or space), keep via aspect ratios below 6:1 and consider through-hole copper thickness of 35 µm or more.

The thermal conductivity of 0.22 W/m·K is low. For power amplifier pallets or designs dissipating more than a few watts, mount the PTFE board onto an aluminum or copper heat sink with thermally conductive adhesive, and use thermal vias under active devices to conduct heat to the ground plane.

Handling and Storage

• Store panels flat in a clean, dry environment. PTFE does not absorb moisture significantly, but copper oxidation still degrades solderability.
• Wear lint-free gloves—fingerprint oils on PTFE surfaces are difficult to remove and degrade bonding adhesion.
• Avoid stacking panels without interleaving paper; PTFE surfaces are soft and scratch easily, which can affect impedance on microstrip traces.

Standards and Specifications

RT/duroid 5870 is tested per Rogers Corporation’s published datasheet using IPC-TM-650 test methods. Finished RT Duroid 5870 PCBs should be qualified to IPC-6012 Class 2 or Class 3 depending on the application tier. For space-grade hardware, additional requirements from NASA-STD-8739.3 soldering standard may apply, particularly regarding via reliability and copper adhesion after thermal shock.

Frequently Asked Questions

Can RT Duroid 5870 be used in multilayer PCBs?

Yes. Multilayer RT Duroid 5870 PCB stackups of 4–8 layers are feasible using Rogers 3001 bonding film or RT/duroid 6202PR prepreg to bond PTFE cores. The key is matching the bonding layer’s Dk (2.28 for 3001 film) closely to the core Dk of 2.33 so that stripline impedance remains predictable across the bonding interface.

What is the maximum frequency for RT/duroid 5870?

The laminate itself performs well through 77 GHz and beyond. The practical frequency limit is set by fabrication tolerances—trace width and gap accuracy—rather than the material. Most production designs use 5870 up to about 40 GHz; above that, tighter-tolerance processes and thinner substrates (5 mil cores) are needed.

How does RT/duroid 5870 compare to RT/duroid 5880?

Both use the same glass-microfiber-reinforced PTFE system. The difference is Dk: 5870 has a Dk of 2.33, while 5880 has a Dk of 2.20 with even lower Df (0.0009). Choose 5870 when your impedance or line-width targets align with Dk 2.33; choose 5880 when minimum loss is the overriding priority.

Is solder mask possible on RT/duroid 5870?

Standard LPI solder mask adheres poorly to PTFE. Most RT Duroid 5870 PCBs ship without mask, using conformal coating or shielding cavities instead. Coverlay film or selective masking over non-PTFE regions of hybrid boards are alternatives.

What bonding film should I use with RT/duroid 5870?

Rogers 3001 bonding film (Dk 2.28, PTFE-based) is the standard choice. For hybrid stackups combining 5870 with FR-4 or polyimide, use a thermoplastic bonding film rated for PTFE adhesion, and expect a Dk discontinuity at the bonding interface that must be modeled in your electromagnetic simulation.