Copper Coin PCB | Embedded Thermal Path for RF Power

What Is a Copper Coin PCB?

A copper coin PCB contains a solid copper slug—typically 1–3 mm thick—press-fit or bonded into a routed pocket in the laminate stack, directly beneath a high-power device such as a GaN PA, LDMOS transistor, or laser diode driver. Because the slug is continuous metal rather than a cluster of thermal vias, it delivers thermal conductivity on the order of 385–400 W/m·K, roughly 10–20× better than a filled-via array through FR-4 (effective ~20–40 W/m·K depending on via density). The coin bridges the gap between the component pad and an external heatsink or metal-core layer, keeping junction temperatures within safe limits even at multi-watt RF power levels.

Why Thermal Vias Alone Fall Short at High Power

Thermal vias are the default heat-extraction method in multilayer PCBs. A 0.3 mm (12 mil) drill with 1 oz plating has a thermal resistance of roughly 70–100 °C/W per via. Even a dense 5×5 array under a QFN pad only brings the combined resistance down to about 3–4 °C/W. For a 10 W GaN device with a maximum junction temperature of 175 °C, that budget disappears fast once you add the die-attach and board-to-heatsink interfaces.

A copper coin, by contrast, presents a nearly homogeneous copper cross-section. A 10 × 10 mm coin that is 1.6 mm thick has a conductive thermal resistance below 0.1 °C/W through the slug itself. The dominant resistance shifts to the solder or epoxy interfaces above and below the coin, which the designer can optimize independently. This is why copper coin PCBs appear in high-power radar transmit modules, base-station PAs, and solid-state microwave ovens.

Copper Coin Construction Methods

Press-Fit (Pre-Lamination)

The coin is machined from C110 or C101 alloy copper, pressed into a routed cavity in the prepreg and core stackup, then laminated under heat and pressure. Resin flows around the coin edges, sealing it in place. This method yields the best coplanarity (±25 µm typical) and the most reliable resin seal, but requires tight tolerances on coin height versus cavity depth—usually ±50 µm (±2 mil).

Post-Lamination Insertion

The board is laminated first, then a pocket is depth-routed from one side and the coin is bonded in with thermally conductive epoxy. This is simpler for prototypes but introduces an epoxy bond line (0.05–0.1 mm) that adds 0.5–1.5 °C/W depending on the epoxy grade. Thermal epoxies with 5–10 W/m·K fillers help, but they still limit the advantage over a well-designed via array.

Hybrid with Metal-Core Layer

Some designs combine a copper coin with a metal-core RF PCB base layer, where the coin is soldered or brazed to the aluminum or copper core. This creates a continuous metal path from die to chassis and is common in high-reliability radar T/R modules.

Stackup Design Rules for Copper Coin PCBs

Integrating a solid copper slug into a multilayer RF stackup introduces mechanical and electrical constraints that do not exist in a standard board.

• Coin-to-trace clearance: Maintain at least 0.25 mm (10 mil) between the coin edge and any signal trace on the same layer to prevent resin-starved areas from degrading impedance control.
• Reference plane continuity: The coin usually replaces part of a ground plane. If the interrupted plane is a return-current reference for a controlled-impedance trace, re-route the trace or add stitching vias around the coin perimeter to restore the return path.
• Prepreg flow: Use high-resin-content prepreg (≥60 % RC) around the coin pocket to fill gaps without voids. Standard 1080 or 2116 glass styles work; avoid low-flow prepregs here.
• Symmetry: Place coins symmetrically about the board midline whenever possible, or add a balancing copper feature on the opposite side, to minimize bow and twist during lamination. IPC-6012 Class 3 limits bow and twist to 0.75 %.
• Surface finish over coin: The coin top pad is typically finished with ENIG or ENEPIG for wire-bondable pads. Bare copper with OSP is possible for reflow-only assemblies but offers limited shelf life.

Return Path Disruption Around the Coin

Embedding a copper coin in a ground plane creates a potential return-path discontinuity. High-frequency return currents mirror the signal trace on the nearest reference plane; if the coin edge or surrounding resin gap interrupts that mirror path, the return current detours around the gap, increasing loop inductance and radiating EMI. At frequencies above a few gigahertz, even a 0.5 mm gap can shift a 50 Ω line by several ohms.

The practical fix is a perimeter ring of ground vias spaced no more than λ/20 apart at the highest operating frequency. For a 10 GHz design on RO4350B (Dk 3.48), λ/20 ≈ 0.8 mm, so via pitch around the coin should be ≤ 0.8 mm. Use the checker below to evaluate whether your current layout risks a return-path break.

If the tool flags a disruption risk, the most effective remediation is to add stitching vias on both sides of any trace that crosses near the coin boundary, connecting the reference planes above and below. In severe cases, re-route the trace so it never crosses the coin edge at all—treat the coin perimeter like a keep-out for controlled-impedance lines.

Copper Balance and Warpage Control

A copper coin adds a large, localized mass of copper—often 2–5 grams in a board that may weigh 20–30 grams total. This asymmetry in copper distribution creates differential CTE stress during lamination and reflow, leading to bow, twist, or delamination if not balanced.

Thick copper RF PCB fabricators already manage heavy copper layers, but a coin concentrates the mass in one spot rather than distributing it across a full layer. Balancing strategies include:

• Adding a dummy copper pad or thieving pattern on the opposite board face, matched in area and thickness to the coin.
• Using symmetrical prepreg layups above and below the coin plane.
• Specifying a post-lamination bake and press cycle to relieve residual stress before drilling.

Check your current design’s copper distribution with the tool below. Enter the coin dimensions and the surrounding copper percentages to see whether warpage risk is within acceptable limits.

A result showing more than 15–20 % copper area imbalance between top and bottom halves of the stackup is a strong indicator that you need balancing copper. Even if the board passes incoming inspection flat, it may warp during reflow when lead-free solder profiles push the board above 245 °C for 60–90 seconds. Addressing balance early avoids costly assembly yield loss.

RF Performance Considerations

Impedance Near the Coin

A copper coin sitting at a ground-plane layer acts as an ideal ground reference directly beneath it—its solid cross-section has lower inductance than a via-stitched plane. Traces routed directly over the coin can actually see a slight impedance drop (1–2 Ω on a 50 Ω line) because the effective ground-plane distance decreases by the resin fill gap. Account for this in your impedance model, and if critical, apply etch compensation to widen the trace slightly over the coin zone.

Grounding and Cavity Resonance

The coin-to-board interface can form a small cavity bounded by the coin top, the surrounding dielectric, and the nearest ground plane. If the cavity’s longest dimension approaches λ/2 at operating frequency, it can resonate and couple energy into nearby traces. For a 10 × 10 mm coin on RO4350B, the first cavity resonance appears around 8 GHz. Filling the perimeter gap with conductive epoxy or adding the via stitching ring described earlier suppresses this mode.

Thermal Effects on Dk

Dielectric constant of most PTFE and hydrocarbon laminates drifts with temperature. Rogers RO4350B has a thermal coefficient of Dk of +50 ppm/°C. Near a copper coin carrying 10 W, local board temperature can reach 80–100 °C, shifting Dk by roughly 0.01—small but measurable in narrowband filter or coupler designs. Simulate with the elevated temperature Dk if your circuit Q is above 50.

Fabrication Checklist

1. Specify coin material (C110 ETP copper is standard; C101 OFE for space or vacuum applications in space-grade RF PCBs).
2. Define coin dimensions with ±50 µm height tolerance and ±25 µm XY positional tolerance.
3. Call out press-fit or epoxy-bonded method on the fabrication drawing.
4. Specify prepreg resin content ≥ 60 % for cavity-fill layers.
5. Add ground-stitching via ring at ≤ λ/20 spacing around coin perimeter.
6. Include copper-balance analysis; add thieving if top-to-bottom imbalance exceeds 15 %.
7. Note surface finish over coin pad (ENIG, ENEPIG, or OSP) and required coplanarity.
8. Request DFM review before release—coin PCBs have non-standard process steps that benefit from early fab feedback.

When to Choose a Copper Coin vs. Alternatives

Choose a copper coin when you need multilayer RF routing capability (controlled impedance, stripline, blind/buried vias) but the power dissipation exceeds what thermal vias can handle. If your device dissipates under 3 W and ambient cooling is adequate, a well-designed via array is cheaper and simpler. If you need more than 50 W through a single site, consider DBC or a brazed coin-on-copper-core hybrid.

Frequently Asked Questions

What copper alloy is used for PCB coins?

C110 (Electrolytic Tough Pitch) is the standard choice, offering 385 W/m·K thermal conductivity at moderate cost. C101 (Oxygen-Free Electronic) is specified for vacuum, space, or cryogenic environments where outgassing must meet NASA ASTM E595 limits.

Can a copper coin be used in a flex or rigid-flex PCB?

Rigid-flex boards can incorporate a coin in the rigid section, but the coin must not span the flex transition zone. The mass and stiffness of the coin would crack the flex layers under bending.

Does a copper coin affect controlled impedance?

Yes. Traces routed directly over the coin see a lower reference-plane distance (by the thickness of the resin fill gap, typically 25–75 µm), which can reduce impedance by 1–3 Ω. Model this in your 2D field solver and adjust trace width or add a clearance keep-out over the coin for sensitive lines.

How much does a copper coin PCB cost compared to standard?

Expect a 30–60 % cost premium over an equivalent board with thermal vias, driven by CNC machining of the coin, the routed cavity, tighter lamination process control, and additional inspection steps. Volume reduces the per-unit premium significantly because the coin machining is amortized.

What IPC standard governs embedded metal objects?

IPC-6012 Rev E covers performance requirements for rigid boards including embedded features. Designers should also reference IPC-2221B Section 6 for thermal management design guidelines applicable to embedded metal slugs.