4 Layer RF PCB: Stackup, Impedance & Fabrication

What Is a 4 Layer RF PCB?

A 4 layer RF PCB is a four-copper-layer printed circuit board engineered for radio-frequency signal integrity. The standard architecture places RF signal traces on the top and bottom layers, a continuous ground plane on Layer 2, and a power or second ground plane on Layer 3. This arrangement gives every microstrip trace an immediate, unbroken reference plane, controls characteristic impedance to within ±5–8 %, and keeps the total board thickness between 0.8 mm and 1.6 mm (roughly 31–63 mil). It is the most common layer count for GPS front ends, Wi-Fi modules, ISM-band radios, and sub-6 GHz 5G small cells.

Why Four Layers for RF?

A two-layer board forces signal and return current to share the same routing space, creating impedance discontinuities and uncontrolled radiation above a few hundred megahertz. A 4 layer RF PCB solves this by providing a dedicated ground reference directly beneath each signal layer. The result is tighter impedance tolerance, lower insertion loss, and a natural EMI shield formed by the inner copper planes. Compared to an 8 layer RF PCB, the four-layer option costs 30–40 % less in laminate and processing, making it the default starting point for any design that can fit its routing into two signal layers.

Standard 4 Layer RF PCB Stackup

The table below shows the most widely used stackup for a 4 layer RF PCB targeting 50 Ω microstrip on the outer layers. Dimensions assume RO4350B cores and FR-4 prepreg for the inner bond, a hybrid approach that keeps cost down while preserving RF performance through 10 GHz.

Total finished thickness lands near 62 mil (1.57 mm). The thin 10 mil RF core keeps the 50 Ω microstrip trace width narrow—approximately 22 mil on RO4350B—so you can route between 0.5 mm-pitch component pads without difficulty. The thicker FR-4 prepreg in the center adds mechanical rigidity and decouples the power plane from ground, providing distributed decoupling capacitance.

Use the stackup builder below to experiment with different core and prepreg thicknesses, dielectric constants, and copper weights. Enter your target impedance and frequency, and it will return the trace width and estimated loss per inch.

If the builder returns a 50 Ω microstrip width of 22.1 mil on a 10 mil RO4350B core, that is a realistic production value. A fabricator can hold this width to ±0.5 mil with standard photo-lithography, yielding impedance within ±2 Ω at 5 GHz. If your design needs tighter control, consider moving to the RF PCB tolerance table to see what process classes are available.

Hybrid vs. Homogeneous Dielectric

A fully homogeneous stackup—all four dielectric layers in the same high-frequency laminate—gives the best Df uniformity and simplifies impedance modeling. But it can double laminate cost. The hybrid approach (RF laminate on outer cores, FR-4 or low-cost prepreg in the center) is the industry workhorse for designs below 10 GHz. Above 10 GHz, the FR-4 center bond’s higher loss tangent (Df ≈ 0.020 vs. 0.004 for RO4350B) starts to matter for stripline traces routed between L2 and L3. At that point, switch to a homogeneous RO4350B or RO3003 build, or move to more layers.

Material Selection for a 4 Layer RF PCB

Rogers RO4350B datasheets confirm a Dk tolerance of ±0.05 at 10 GHz, which is tight enough that many engineers skip the test-coupon verification step for production below 6 GHz. For 24 GHz automotive radar or K-band links, RO3003’s lower Df delivers roughly 0.5 dB less loss per inch of microstrip at 24 GHz compared to RO4350B—a significant margin when the entire RF chain budget may be only 3–4 dB.

Impedance Control on a 4 Layer RF PCB

Characteristic impedance depends on trace width, dielectric thickness, copper weight, and the dielectric constant of the material between the trace and its reference plane. On a 4 layer RF PCB, the dominant transmission-line mode is microstrip (L1 or L4 trace over L2 ground). Coplanar waveguide with ground (CPWG) is the second most common, used when you need tighter coupling or want to add ground coplanar fingers beside the trace to improve isolation.

Microstrip Design Rules

• 50 Ω single-ended: ~22 mil trace on 10 mil RO4350B (½ oz copper, no solder mask).
• 100 Ω differential: ~12 mil traces, 8 mil gap on the same stackup.
• Solder mask effect: adding LPI solder mask (Dk ≈ 3.3–3.8) over a microstrip lowers impedance by 2–4 Ω. Either widen the trace or specify mask openings over RF lines.
• Copper roughness: standard oxide treatment (Rz ≈ 5–6 µm) adds measurable loss above 10 GHz. Request reverse-treated foil (RTF) or very-low-profile (VLP) foil (Rz < 2 µm) for Ka-band work.

Try adjusting trace width and dielectric thickness in the impedance matching game below. It visualizes how each parameter shifts the impedance, helping you build intuition faster than running a field solver repeatedly.

If the game shows that moving from a 10 mil to an 8 mil core drops your 50 Ω trace width from 22 mil down to 17 mil, that is correct—and it means your minimum space-and-trace rules tighten. Verify that your component land patterns still allow the narrower trace before committing to a thinner core. For designs that outgrow two signal layers, an eight-layer hybrid multilayer adds dedicated stripline routing without changing the outer-layer geometry.

Fabrication Considerations

Drilling and Vias

Through-hole vias on a 4 layer RF PCB are straightforward—a 0.3 mm (12 mil) drill through a 1.57 mm board gives an aspect ratio of roughly 5:1, well within standard capability. The concern is via stubs. A via connecting L1 to L2 still has a stub extending from L2 to L4. At 5 GHz the stub’s quarter-wave resonance sits around 7.5 GHz (assuming an effective Dk of 3.5), which may fall inside your second harmonic. Two solutions: use blind vias (L1–L2 only) via blind and buried via processing, or specify back drilling to remove the stub down to 8–10 mil below L2.

Copper Plane Integrity

The L2 ground plane must be as unbroken as possible. Every split, slot, or missing via-pad clearance that crosses under an RF trace creates an impedance discontinuity. Route all non-RF signals on L4 or through the power plane on L3, and stitch the ground plane with vias at λ/20 spacing (for example, every 60 mil at 10 GHz). Power connections on L3 should use a star or spoke topology that does not cut a return-current path under any RF line on L1.

Surface Finish

ENIG (electroless nickel / immersion gold) is the default for RF boards because the gold prevents copper oxidation and the nickel barrier is thin enough (3–5 µm) that skin-effect losses stay manageable below 10 GHz. Above 20 GHz, the nickel’s ferromagnetic loss becomes significant; switch to immersion silver or OSP, or specify ENEPIG with a thinner nickel layer. Designs with edge-launch connectors or high-cycle test pads may benefit from hard gold plating on those specific features.

Registration and Tolerance

Layer-to-layer registration on a 4 layer board is typically ±3 mil (75 µm). For CPWG traces where the gap between the signal trace and coplanar ground defines impedance, a 3 mil shift can change impedance by 1–2 Ω. Specify ±2 mil registration if your design uses CPWG at frequencies above 6 GHz, and confirm the fabricator can meet it on your chosen laminate. Consult IPC-6012 Class 3 for the tightest standard performance tier.

Design Checklist for a 4 Layer RF PCB

1. Define your highest operating frequency. This sets the laminate grade, copper roughness class, and whether you need blind vias or back drilling.
2. Choose homogeneous or hybrid dielectric. Below 10 GHz, hybrid (RF core + FR-4 bond) saves 25–40 % on material. Above 10 GHz, go homogeneous.
3. Set core thickness for target impedance. Run the stackup builder with your Dk, copper weight, and 50 Ω target. Confirm the resulting trace width fits your pad geometry.
4. Keep L2 ground continuous. No splits under RF traces, via stitching at λ/20, and power routed on L3 only.
5. Specify solder-mask openings over all impedance-controlled RF traces, or model the mask’s Dk into your impedance calculation.
6. Select surface finish by frequency. ENIG below 10 GHz, immersion silver or OSP above 20 GHz.
7. Call out impedance coupons. Require TDR test coupons on the production panel; ±5 % tolerance for Class 2, ±3 % for Class 3.
8. Document stackup in fabrication notes. Include material callouts, target Dk at frequency, copper weights, and finished board thickness. A stackup design service can validate this before you release Gerbers.

When to Move Beyond Four Layers

A 4 layer RF PCB runs out of room when you need more than two RF signal layers, embedded stripline for better shielding, or dense digital buses alongside the RF section. Typical upgrade triggers:

• Routing density: more than ~200 RF nets that cannot be completed on two layers.
• Mixed RF + digital: high-speed SERDES, DDR4/5 memory, or FPGA I/O that demand their own impedance-controlled stripline layers.
• Isolation: a transmitter and receiver on the same board above 6 GHz, where buried stripline layers between ground planes offer 20–30 dB more isolation than microstrip.

For phased-array feed networks, power-divider trees, or multi-band transceivers, an 12 layer microwave stackup provides the additional shielded routing layers without compromising the RF performance established on the outer layers.

FAQ

Can FR-4 be used for a 4 layer RF PCB?

Yes, for frequencies below about 1–2 GHz. Standard FR-4 has a Df of 0.018–0.020 at 1 GHz, which is acceptable for Bluetooth, sub-GHz ISM, and basic GPS patch antennas. Above 2 GHz, loss and Dk variation with frequency make FR-4 unreliable for impedance-controlled RF lines.

What is the typical lead time for a 4 layer RF PCB prototype?

Prototypes on RO4350B with standard ENIG finish typically ship in 5–7 working days. Hybrid builds with PTFE cores (RO3003, RT/duroid) may add 2–3 days due to plasma desmear and specialized drilling. Expedited options can reach 3 days for non-PTFE laminates.

How does copper weight affect RF loss?

Thicker copper (1 oz vs. ½ oz) reduces resistive loss because the conductor cross-section is larger, but the improvement is modest above 3 GHz where skin effect confines current to the outer few micrometers. The bigger impact of copper weight is on trace geometry: thicker copper requires wider etch compensation, which changes the final trace width and therefore impedance. Always specify finished copper weight in your impedance calculation.

Is back drilling necessary on a 4 layer board?

Only if the via stub resonance falls within or near your operating band. On a 62 mil board, a full through-via stub from L2 to L4 is about 50 mil long, resonating near 15 GHz (quarter-wave in Dk ≈ 3.5). For 5 GHz Wi-Fi this is safely out of band. For 10 GHz X-band radar, the stub’s effect starts to appear as a notch in S21, and back drilling or blind vias become worthwhile. Refer to Isola’s Astra MT77 design guide for via-stub modeling examples applicable to high-frequency four-layer builds.