TR Module PCB Design for Phased Arrays

What Is a TR Module PCB?

A TR module PCB is the multilayer substrate that integrates a power amplifier (PA), low-noise amplifier (LNA), phase shifter, attenuator, T/R switch, and associated bias and control circuitry into a single, repeatable building block for an active electronically scanned array (AESA). Each element in the array gets its own T/R module, so the PCB must deliver consistent RF performance, efficient heat removal, and precise dimensional repeatability across hundreds or thousands of units. Operating frequencies range from L-band (1–2 GHz) for ground-based surveillance radars up through Ka-band (26.5–40 GHz) for satcom and beyond into W-band (75–110 GHz) for automotive and millimeter-wave imaging.

The substrate is arguably the most critical passive component in the module. It sets insertion loss, impedance accuracy, thermal resistance from die to heatsink, and the mechanical envelope that determines array lattice spacing. Getting the TR module PCB wrong cascades into degraded beam patterns, reduced transmit power, higher noise figures, and shortened field life.

Key Performance Requirements for a TR Module PCB

RF Signal Integrity

Transmit paths typically carry 2–10 W per element at X-band, while receive paths must preserve noise figures below 2.5 dB. The PCB must support controlled-impedance transmission lines—microstrip, stripline, or coplanar waveguide—with impedance tolerance within ±5 % and insertion loss low enough that the PA’s output power is not wasted before reaching the radiating element. At X-band (8–12 GHz), every 0.1 dB of excess line loss across the module reduces effective radiated power by roughly 2.3 %, directly impacting radar range.

Thermal Management

GaN PA die can dissipate 5–15 W in a footprint of 3 × 4 mm. Junction temperatures must stay below 175 °C for reliable operation, so the substrate’s through-thickness thermal conductivity matters enormously. Organic laminates like Rogers RO4350B offer about 0.69 W/m·K, while alumina-based LTCC (low-temperature co-fired ceramic) reaches 2–3 W/m·K, and aluminum nitride (AlN) substrates exceed 170 W/m·K. The choice between these materials is often the single biggest architectural decision in TR module PCB design.

Dimensional and Phase Matching

In a phased array, element-to-element phase error must be held below 5–10° RMS for acceptable sidelobe performance. Because transmission-line phase is proportional to electrical length, the PCB must deliver tight control of dielectric constant (Dk) tolerance (±1.5 % or better), trace width (±0.5 mil / ±12.5 µm), and overall module-to-module dimensional repeatability. Any drift in Dk across a production lot shifts the phase of every line on the board.

Substrate Technology Comparison

Three substrate families dominate TR module PCB construction. The table below compares them across the parameters that matter most.

Choose organic when the frequency is below Ku-band, power dissipation per element is under ~5 W, and cost per module must stay low for large-quantity arrays. Choose LTCC when you need embedded passives, hermetic or near-hermetic packaging, and operation into Ka-band. Choose AlN or alumina thin-film for the highest power densities and millimeter-wave frequencies where line-width resolution and thermal conductivity are non-negotiable.

Stackup Architecture for Organic TR Module PCBs

A typical organic TR module PCB uses 12–24 layers in a hybrid stackup that combines low-loss RF laminates for signal layers with high-Tg FR-4 or polyimide for digital control and DC bias layers. A representative X-band stackup might look like this:

• Layer 1 (top): RF signal — microstrip PA output, LNA input, antenna feed. Material: Rogers RO4350B (Dk 3.48, Df 0.0037 at 10 GHz).
• Layer 2: Ground plane — continuous copper, stitched with via fences to isolate transmit and receive channels.
• Layers 3–4: Stripline RF — phase shifter traces and coupler networks buried between ground planes for shielding.
• Layers 5–6: Ground / power — split power planes for PA drain, LNA drain, and digital supply, separated by capacitance-optimized dielectric.
• Layers 7–10: Digital control — SPI/serial buses to the beamformer ASIC, FPGA I/O, and attenuator control lines.
• Layers 11–12: Thermal / structural — thick copper or coin-embedded layers directly beneath the PA die for heat extraction.

The key rule is to keep RF layers on low-loss laminate with dedicated ground references, and never route high-speed digital signals on the same dielectric layer as an RF trace. Via transitions between RF layers should use back-drilled or controlled-depth vias to eliminate stubs that create resonances. At X-band, a 20-mil (0.5 mm) via stub can produce a quarter-wave resonance near 30 GHz—outside the operating band but close enough to degrade wideband performance and complicate RF test fixture calibration.

Thermal Via and Coin Strategies

For GaN PA die generating 10 W in a 4 × 4 mm footprint, the thermal path through the TR module PCB to the cold plate is the bottleneck. Two common approaches exist:

Thermal Via Arrays

Drilling a dense array of plated vias (typically 10-mil diameter, 20-mil pitch) beneath the die pad reduces the effective through-board thermal resistance. A 100-via array under a 4 × 4 mm pad in a 62-mil (1.6 mm) board can bring thermal resistance down to roughly 5–8 °C/W, compared to 40+ °C/W for bare laminate. Fill the vias with copper or thermally conductive epoxy and cap-plate them for a solderable surface.

Embedded Copper Coins

Press-fitting a solid copper slug (coin) into a routed pocket in the PCB provides a direct metal path from the die attach pad to the backside heatsink. Thermal resistance drops below 1 °C/W for a well-designed coin. The trade-off is added fabrication complexity: the coin pocket must be milled to ±1 mil tolerance, and the CTE mismatch between copper (17 ppm/°C) and the surrounding laminate must be managed with stress-relief features to prevent delamination over thermal cycling.

Isolation and Compartmentalization

A TR module PCB switches between transmit (high power) and receive (high sensitivity) modes, sometimes with 60–80 dB of isolation required between the two paths. The PCB contributes to this isolation through:

• Via fencing: Rows of ground vias spaced at λ/20 or closer surround each RF trace and create a pseudo-waveguide wall. At 10 GHz (λ ≈ 30 mm in free space, ~17 mm in RO4350B), via pitch should be ≤ 0.85 mm.
• Embedded shielding cavities: Internal copper walls formed by stitched via rows plus top and bottom ground planes create Faraday-cage compartments around the PA and LNA.
• Split ground planes: Separate ground islands for the transmit and receive sections, connected only at a single-point star ground, prevent common-mode coupling through shared return currents.

These techniques are the same ones used in circulator and isolator PCBs, scaled to the module’s smaller footprint and higher density.

Fabrication and Assembly Challenges

Mixed-Material Lamination

Hybrid stackups that bond PTFE-based RF laminates to FR-4 or polyimide cores require careful prepreg selection. Rogers CuClad or Isola Astra MT77 prepregs are designed for this purpose, but their flow characteristics differ from standard FR-4 prepreg. Lamination pressures and temperature profiles must be qualified for each combination. Isola’s Astra MT77 data sheet provides recommended press cycles for hybrid builds.

Die Attach and Wire Bonding

Many T/R modules use bare-die GaN or GaAs MMICs attached directly to the PCB with conductive epoxy or AuSn solder. The substrate surface must be flat to within 25 µm across the die attach area, and the finish must support wire bonding—typically electroless nickel / immersion gold (ENIG) or electrolytic hard gold (≥ 30 µin / 0.76 µm). Soft gold bondable surfaces require careful specification per IPC-4552 for ENIG to avoid black-pad defects that compromise bond reliability.

Hermeticity and Environmental Protection

Military and space T/R modules often require hermetic sealing to MIL-STD-883 standards. Organic PCBs are inherently non-hermetic, so they rely on glob-top encapsulants, conformal coatings, or a separately sealed lid over the MMIC cavities. LTCC substrates can achieve true hermeticity through co-fired seal rings and brazed lids.

TR Module PCB Applications Beyond Radar

While AESA radar remains the primary driver, TR module PCBs appear in a growing range of systems:

• 5G massive-MIMO base stations: 64–256 element arrays at 28 GHz or 39 GHz, using organic substrates to meet commercial cost targets. The PA stages in these modules share design DNA with Doherty amplifier boards optimized for efficiency.
• LEO satcom terminals: Flat-panel electronically steered antennas for Starlink, OneWeb, and similar constellations, operating at Ku/Ka-band.
• Electronic warfare (EW): Wideband T/R modules spanning 2–18 GHz for jamming and signal intelligence, demanding ultra-broadband transitions and low-dispersion substrates.
• Medical imaging: Ultrasound phased arrays and emerging MRI coil arrays where per-element T/R switching is moving onto PCB substrates.

The full range of board-level RF applications, from radar to communications to medical, is cataloged in the RF PCB applications overview.

Design Checklist for TR Module PCBs

1. Define the operating frequency, instantaneous bandwidth, and transmit power per element before selecting a substrate.
2. Run a thermal simulation (Ansys Icepak, 6SigmaET, or similar) to determine whether thermal vias, copper coins, or a ceramic substrate are needed to keep junction temperatures within budget.
3. Specify Dk tolerance ≤ ±1.5 % and request incoming inspection data from the laminate vendor for each lot.
4. Design via fences at λ/20 spacing around every RF trace and between transmit and receive channels.
5. Use back-drilling or controlled-depth drilling to eliminate via stubs longer than λ/20 at the highest frequency of interest.
6. Qualify the hybrid lamination process with cross-section analysis and peel-strength testing per IPC-6012 Class 3/A for military or IPC-6012 Class 3 for high-reliability commercial.
7. Specify wire-bondable gold finish thickness and pull-test requirements on the fabrication drawing.
8. Include test coupons for impedance verification, insertion-loss measurement, and thermal-via resistance on every production panel.

Frequently Asked Questions

What is the typical layer count for a TR module PCB?

Most organic TR module PCBs use 12–24 layers. High-integration phased-array boards that combine multiple T/R channels on a single tile can reach 40 layers. LTCC modules routinely use 10–60 co-fired layers because each layer is only 4–10 mil (100–250 µm) thick.

Can FR-4 be used for a TR module PCB?

FR-4 is generally unsuitable for the RF signal layers because its Df of 0.020 at 10 GHz introduces excessive insertion loss and its Dk tolerance (often ±10 %) makes phase matching impractical. FR-4 can serve as the digital and power-distribution core in a hybrid stackup, with low-loss laminates handling the RF layers.

How does GaN affect TR module PCB design compared to GaAs?

GaN PAs deliver 3–5× higher power density than GaAs at the same frequency, which increases the thermal load on the substrate. GaN modules almost always require copper coins or ceramic substrates, whereas lower-power GaAs modules can sometimes get by with dense thermal-via arrays on organic boards. GaN also operates at higher drain voltages (28–50 V vs. 5–8 V for GaAs), so the bias distribution planes must handle higher voltage with appropriate clearance.

What surface finish is best for wire-bonding on a TR module PCB?

Electrolytic hard gold (≥ 30 µin) over nickel is the most reliable finish for gold-ball or gold-wedge wire bonding. ENIG can work if the nickel phosphorus content is tightly controlled (mid-phosphorus, 6–9 % P) and the gold thickness is at least 3 µin, but it carries a higher risk of brittle fracture at the bond interface under thermal cycling.