LDMOS Amplifier PCB | Broadcast & Base Station

What Is an LDMOS Amplifier PCB?

An LDMOS amplifier PCB is the printed-circuit board that carries a laterally-diffused metal-oxide-semiconductor (LDMOS) power transistor together with its input and output matching networks, bias circuitry, and thermal-management structures. LDMOS devices dominate solid-state power amplification from roughly 1 MHz to 2.7 GHz, delivering hundreds of watts per die at drain efficiencies above 60 %. The PCB must present extremely low-impedance matching transformations—often from the sub-ohm device plane to 50 Ω—while sinking 50–200 W of heat per transistor. Getting the board wrong means poor efficiency, gain compression, or outright device failure.

These boards are the backbone of FM/TV broadcast transmitters, cellular base station power amplifiers, pulsed radar drivers, and ISM heating systems. The discussion below walks through every layer of the design—substrate, stackup, matching topology, thermal path, bias network, and test—so you can specify or review an LDMOS amplifier PCB with confidence.

Where LDMOS Amplifier PCBs Are Used

Broadcast Transmitters

FM radio (87.5–108 MHz) and UHF television (470–862 MHz) transmitters stack multiple LDMOS pallets into combiners to reach kilowatt-class output. Each pallet is a self-contained LDMOS amplifier PCB running 300–600 W. Reliability over 100 000 hours of continuous keying is non-negotiable, so the board must tolerate load VSWR up to 10:1 without destroying the device.

Cellular and 5G Base Stations

Macro-cell remote radio units (RRUs) at 700 MHz through 2.7 GHz use LDMOS final stages, sometimes in Doherty amplifier configurations for back-off efficiency. Average power per carrier path is typically 20–60 W, but peak power can exceed 250 W under high crest-factor signals like 5G NR OFDM.

Other RF Power Applications

Pulsed L-band and S-band radar, ISM 13.56 MHz plasma generators, and MRI gradient amplifiers all exploit LDMOS ruggedness. The board-level challenges—low-impedance matching, heat removal, bias sequencing—are shared across every application, though frequency and duty cycle shift the emphasis. A broader survey of power-amplifier and signal-chain boards is available in the RF PCB applications overview.

Substrate Selection for LDMOS Power Amplifiers

The substrate must satisfy three demands simultaneously: low dielectric loss at the operating frequency, high thermal conductivity to move heat from the device flange into the heatsink, and dimensional stability under sustained thermal cycling.

For most LDMOS amplifier PCBs below 3 GHz, RO4350B on 30 mil (0.762 mm) or 60 mil (1.524 mm) thickness is the default choice. Its thermoset resin processes on standard FR-4 equipment, keeping fabrication cost lower than PTFE alternatives. When the matching-network Q must be higher—common in narrow-band broadcast designs—RT/duroid 5880 or alumina substrates are justified despite their higher cost and more fragile handling. Rogers RO4350B datasheet provides the full Dk-versus-frequency curve designers need for simulation.

Why FR-4 Fails at High Power

Standard FR-4 (Dk ≈ 4.3–4.8, Df ≈ 0.020 at 1 GHz) introduces excessive dielectric loss in the matching network, which at 100 W translates directly into board heating and efficiency loss. Its glass-transition temperature (Tg ≈ 130–170 °C) also risks delamination near the device flange. FR-4 is acceptable only for the bias and control sections of the pallet, not the RF path.

Stackup and Layer Strategy

Most LDMOS amplifier PCBs are two-layer or four-layer designs. The RF matching network sits on the top copper with a continuous ground plane on layer 2, backed by a metal carrier (copper-molybdenum-copper or aluminum). A four-layer board adds a buried bias-distribution plane and a second ground, useful when digital predistortion (DPD) feedback or complex bias sequencing shares the same assembly.

• Layer 1 (top): RF traces, matching stubs, DC bias pads, device land pattern.
• Layer 2: Unbroken ground reference. No splits under the RF path—ever.
• Layer 3 (optional): Bias routing, gate-voltage distribution, thermistor sense lines.
• Layer 4 (optional): Additional ground or heatsink attach plane.

Copper weight on the RF layer is typically 1 oz (35 µm) or 2 oz (70 µm). Heavier copper helps carry DC drain current—an LDMOS running 300 W at 50 V draws 6 A or more—but widens the minimum etch resolution. For traces that are already several millimeters wide (common at VHF), 2 oz copper is the better trade.

Impedance Matching: From Sub-Ohm to 50 Ω

The fundamental challenge of any LDMOS amplifier PCB is impedance transformation. A 300 W LDMOS device at 2 GHz presents an optimum load impedance in the range of 1–3 Ω with significant reactive components. The output matching network must transform this to 50 Ω in two or three stages while maintaining bandwidth, managing harmonic terminations, and surviving the RF currents involved.

Matching Topologies

1. Stepped-impedance microstrip: A cascade of quarter-wave (λ/4) or shorter transmission-line sections of decreasing width. Simple, broadband, but physically large below 1 GHz.
2. Lumped-distributed hybrid: Shunt capacitors (often ATC 100B or Murata GRM series) combined with high-impedance line sections. Compact and tuneable, the go-to for base station PAs.
3. Integrated pre-match inside the package: Many modern LDMOS packages (e.g., NXP MRF1K50H, Ampleon BLF188XR) include bond-wire and MOS-cap pre-matching that raises the reference-plane impedance to 5–10 Ω, easing the PCB designer’s job significantly.

Regardless of topology, the PCB traces in the first matching section carry enormous RF current. A 300 W device at 2 Ω means peak currents above 17 A. Trace width, copper weight, and solder-joint quality at the device flange are all critical.

Harmonic Termination

Class-AB and Class-F LDMOS amplifiers need controlled terminations at the second and third harmonics to shape the drain waveform for efficiency. Short-circuit stubs at 2f₀ and open-circuit stubs at 3f₀ are placed close to the device output. These stubs must be modeled with full electromagnetic (EM) simulation—ideally in Keysight ADS Momentum, Ansys HFSS, or Cadence AWR Microwave Office—because fringing, via inductance, and substrate dispersion shift their resonance significantly from ideal.

Thermal Management on the PCB

An LDMOS device dissipating 100 W as heat must transfer that energy through the PCB into the heatsink without exceeding the junction temperature limit (typically 225 °C for silicon LDMOS). The thermal path has three segments: die-to-flange (set by the package), flange-to-board, and board-to-heatsink.

Thermal Via Arrays

Under the device flange, a dense array of plated-through vias connects the top ground pad to the bottom copper and the heatsink below. Effective thermal via design follows these rules:

• Via diameter: 0.3–0.5 mm (12–20 mil) drilled, plated to ≥ 25 µm copper wall thickness.
• Pitch: 0.8–1.0 mm center-to-center for mechanical strength; tighter pitch improves thermal conductivity but risks drill breakout on thin laminates.
• Fill: Copper-filled (plugged and capped) vias reduce thermal resistance by roughly 40 % compared to open vias. Conductive-epoxy fill is a lower-cost alternative but offers only modest improvement.
• Coverage: The via array must cover the entire device source/flange pad, not just the center.

A 10 × 10 array of 0.4 mm copper-filled vias through 0.762 mm RO4350B yields a thermal resistance of approximately 1.5–2.0 °C/W, adequate for devices up to about 150 W per pad. For higher power, designers move to coin-insert technology—a solid copper slug press-fit into a routed pocket in the PCB—which drops thermal resistance below 0.5 °C/W.

Heatsink Attach

The PCB is typically soldered or bolted to an aluminum or copper-molybdenum-copper (CuMoCu) carrier. Solder attach (using SAC305 or indium-based alloys) gives the lowest interface thermal resistance (< 0.1 °C/W per cm²) but demands flatness control to ± 50 µm across the device footprint. Thermal grease or phase-change pads are acceptable for lower-power pallets.

Bias Network and Decoupling

LDMOS devices require a negative gate voltage (typically −2 to −5 V for Class AB) applied before the positive drain supply (28 V or 50 V). The PCB must enforce this sequencing through the layout or an on-board sequencer IC. Key layout rules:

• Gate bias feed: A high-impedance (λ/4 at f₀) microstrip line or a ferrite-loaded choke isolates the RF path from the DC supply. Place the decoupling capacitors (100 pF, 10 nF, 100 nF, 10 µF in parallel) at the choke landing, not at the device pin.
• Drain bias feed: Similar λ/4 choke topology, but the line must carry full DC current (several amperes). Use wide traces (≥ 3 mm) and low-ESR electrolytics close to the board edge connector.
• Video bandwidth: For wideband modulated signals (5G NR, DVB-T2), the bias network must present low impedance down to baseband frequencies (< 1 MHz) to avoid memory effects that degrade linearity. A bank of electrolytic capacitors (22–100 µF) in parallel with RF-grade ceramics achieves this.

Isolating the sensitive gate bias from high-current drain transients is essential. Route the two supplies on opposite sides of the device, and never share a return-current via between them.

Board-Level Integration: Couplers, Circulators, and Filters

A complete LDMOS power-amplifier pallet often integrates directional couplers for power monitoring, circulators or isolators for load protection, and low-pass harmonic filters on the same PCB or a closely mated daughter board. The circulator and isolator PCB section discusses ferrite-integration techniques relevant to LDMOS output stages. Similarly, output harmonic filters in broadcast transmitters frequently use cavity filter assemblies bolted directly to the amplifier module frame.

Fabrication and Assembly Checklist

Before releasing an LDMOS amplifier PCB to fabrication, verify every item below:

1. Substrate Dk tolerance: Confirm the laminate vendor specifies Dk to ± 0.05 or better at your operating frequency. Request lot-specific Dk test data for critical builds.
2. Copper plating on thermal vias: Specify ≥ 25 µm plating and copper fill if needed; call it out on the fabrication drawing per IPC-6012 Class 3 requirements.
3. Surface finish: ENIG or immersion silver for wire-bondable pads; HASL is acceptable for solder-attach flanges but not for fine-pitch matching-network pads.
4. Flatness: ± 50 µm (2 mil) across the device mounting area. Specify in the drawing; not all shops hold this without being told.
5. Solder-mask clearance: Keep solder mask at least 0.25 mm (10 mil) back from the device flange pad and the first matching-network trace to avoid dielectric loading shifts.
6. Assembly: LDMOS devices are typically hand-placed and reflowed or bolted with screws and thermal compound. Ensure the assembly house has RF power-device experience and can torque flange screws to the vendor’s spec (often 0.5–0.9 N·m).
7. RF test: Define pass/fail criteria for gain, output power at P1dB, drain efficiency, and return loss at the board level. Include a test-coupler tap point in the layout.

Common Design Pitfalls

• Ground-plane slot under the output match: Even a narrow slot for a trace crossing creates an inductance that detunes the sub-ohm match and can cause oscillation.
• Insufficient via stitching at package ground tabs: Every source pad and exposed ground tab needs its own cluster of vias; sharing vias between adjacent pads raises common-lead inductance.
• Ignoring substrate Dk variation with temperature: RO4350B shifts roughly +50 ppm/°C in Dk. At 100 °C board temperature, a 2 GHz quarter-wave stub detunes by several MHz—enough to degrade harmonic termination.
• Bias-line resonance: A drain bias choke that resonates within the operating band creates a high-impedance node that clips the drain waveform. Simulate the bias network S-parameters out to 3× f₀ before layout.

Frequently Asked Questions

Can I use FR-4 for an LDMOS amplifier PCB?

Only for the bias, control, and digital sections. The RF matching network must use a low-loss, thermally stable laminate such as RO4350B or RO4003C. FR-4’s high dissipation factor (Df ≈ 0.020) wastes power and heats the board near the device, and its Dk variation is too large for repeatable matching.

What is the maximum frequency for LDMOS power amplifiers?

Silicon LDMOS is practical up to about 3.5 GHz, with most commercial parts optimized for bands below 2.7 GHz. Above that, GaN HEMT technology offers superior gain and efficiency. Some LDMOS devices serve L-band radar (1.2–1.4 GHz) at over 1 kW pulsed.

How do I reduce thermal resistance through the PCB?

Use copper-filled thermal vias on a tight pitch (≤ 1 mm) under the entire device flange, choose a thinner laminate (20–30 mil), and consider a press-fit copper coin for dissipations above 150 W. Solder-attaching the PCB to a CuMoCu carrier further lowers the total junction-to-heatsink resistance.

What surface finish is best for LDMOS flange attach?

Immersion silver or ENIG are preferred for consistent solderability and wire-bond compatibility. OSP is acceptable if the board will be assembled quickly after fabrication. Avoid thick HASL on fine-pitch matching-network pads because the uneven surface shifts trace impedance.

Do I need EM simulation for the matching network?

Yes. Lumped-element and ideal-transmission-line models underestimate parasitic coupling, via inductance, and fringing at the wide, closely spaced traces typical of LDMOS output networks. Full-wave EM simulation (Method of Moments or FEM) is essential for first-pass success, especially above 1 GHz.