RF PCB Stackup Design: Free Service with Every RFQ

Why RF PCB Stackup Design Determines Board Performance

RF PCB stackup design is the single most consequential decision in any high-frequency board project. The layer count, dielectric materials, copper weights and reference-plane placement together set your characteristic impedance, insertion loss per unit length, isolation between signal layers, and thermal behavior. Get the stackup wrong and no amount of trace-tuning or post-layout optimization will recover the performance.

Unlike digital boards where a generic four-layer FR-4 stackup covers most cases, RF and microwave designs demand material-specific dielectric constants (Dk), dissipation factors (Df), and tightly held laminate thicknesses. A 77 GHz automotive radar front-end on RO3003 (Dk 3.00 ± 0.04) needs a fundamentally different stackup philosophy than a 2.4 GHz IoT radio on Megtron 6 (Dk 3.71 ± 0.04). This guide walks through the decisions, trade-offs and deliverables so you can specify—or review—a stackup with confidence.

Core Decisions in an RF Stackup

1. Layer Count and Signal-Plane Topology

The minimum useful RF stackup is two layers: a signal layer over a continuous ground plane, forming a microstrip. This works well for single-band front-ends below about 6 GHz where cost and simplicity dominate. Move to four layers and you gain a buried stripline option—signal sandwiched between two ground planes—which provides inherently better shielding and tighter impedance tolerance at the cost of higher Dk sensitivity and additional lamination cycles.

Six- and eight-layer hybrid stackups are common in radar PCB stackup designs that combine an RF front-end (top two layers on low-loss laminate) with a digital/power section (inner layers on FR-4 or mid-Dk material). The key rule: every RF signal layer must have an unbroken reference plane on the immediately adjacent layer, with no splits or routing crossing the return-current path.

2. Material Selection and Dk/Df Targets

Material choice drives loss, impedance stability over temperature, and cost. The table below compares five laminates frequently specified in RF stackups:

A hybrid stackup that places RO4350B only on the RF signal layers and uses standard FR-4 for the rest can cut material cost by 40–50 % compared with an all-RO4350B build, while keeping RF performance intact. The trade-off is a more complex lamination process—different prepreg systems, CTE mismatch management, and careful registration between dissimilar materials. This is exactly where a fabricator’s stackup design service earns its value.

3. Dielectric Thickness and Impedance Control

For a 50 Ω microstrip on RO4350B (Dk 3.48) with 1 oz (35 µm / 1.4 mil) copper, the required dielectric height is roughly 10 mil (0.254 mm) for a trace width near 22 mil (0.56 mm). Shift to RO3003 (Dk 3.00) and the same 50 Ω target needs about 8 mil dielectric for a 20 mil trace—thinner core, narrower line, tighter etch tolerance. These numbers interact with copper roughness (typically 0.5–1.8 µm RMS on ED copper) which adds effective loss at mmWave frequencies.

An impedance modeling service that runs Polar Si9000 or HFSS-based field solvers on the actual proposed stackup is the only reliable way to lock down trace geometry before layout. Relying on handbook formulas alone introduces 5–10 % impedance error above 10 GHz because they ignore conductor roughness, solder-mask loading, and trapezoidal etch profiles.

4. Copper Weight and Surface Finish

Half-ounce (18 µm) copper is preferred for fine-pitch RF traces because it produces a more rectangular etch profile and less undercut. One-ounce copper is common for ground planes and power distribution. For frequencies above 30 GHz, rolled or very-low-profile (VLP) electrodeposited copper with surface roughness below 1.0 µm RMS measurably reduces conductor loss—by as much as 0.15 dB/inch at 77 GHz compared with standard ED foil.

Surface finish matters too. ENIG adds a thin nickel barrier (typically 3–6 µm) that is lossy at microwave frequencies. Immersion silver or OSP are lower-loss alternatives for RF signal pads, while ENEPIG may be required for wire-bond or mixed-assembly boards. The stackup drawing should call out finish explicitly so the fabricator can account for its effect on impedance and loss.

Hybrid Stackup Architecture: Mixing Materials

Most production RF boards above four layers are hybrids. The principle is simple: use the expensive low-loss laminate only where RF energy travels, and fill the rest with cost-effective material. A typical six-layer hybrid for a 77 GHz radar module might look like this:

• L1 (Top signal): RO3003, 5 mil core — mmWave antenna and transmission lines
• L2 (Ground): Continuous copper, bonded to L1 core
• L3 (Signal/power): FR-4, 8 mil prepreg below L2
• L4 (Ground): Continuous copper
• L5 (Signal/power): FR-4, 8 mil prepreg
• L6 (Bottom signal): FR-4, 5 mil core — digital, SPI, power

The bond between L2 and L3 is the critical interface. Rogers offers RO4450F fusion-bonding prepreg specifically for joining PTFE-based RF layers to FR-4, with a Dk of 3.52 and flow characteristics matched to standard lamination pressures. Using the wrong bonding film here can introduce delamination risk or uncontrolled Dk variation in the transition zone.

For boards requiring all-PTFE construction—such as bonded multilayer PTFE assemblies—the fabricator uses fusion bonding or sodium-etch surface preparation to achieve reliable copper-to-PTFE adhesion across every interface.

What a Stackup Design Service Actually Delivers

A professional RF stackup design service is not just a layer drawing. The deliverable package typically includes:

1. Stackup cross-section drawing — layer order, material callouts, nominal and tolerance thicknesses for every dielectric, copper weights, and finished board thickness.
2. Impedance table — target impedances (50 Ω single-ended, 100 Ω differential, etc.) with modeled trace widths, spacings, and the solver used.
3. Material data references — specific laminate part numbers and IPC-4101 slash-sheet designators so procurement and incoming QC can verify incoming material.
4. DFM notes — minimum annular ring, via aspect ratio limits, back-drill requirements, registration tolerances for hybrid bonds, and any process constraints.
5. Loss estimate — expected insertion loss per inch at the operating frequency for each signal-layer configuration, accounting for conductor roughness and Df.

This package saves weeks of back-and-forth between design and fabrication. When included free with every RFQ, it also means the quoted price and lead time are based on a buildable, verified stackup rather than an assumption.

Export Your Stackup as a Controlled Document

Once the stackup is finalized, you need a version-controlled PDF that can be attached to your fabrication drawing, shared with your EDA tool for impedance-driven routing, and archived with your design release. Use the tool below to generate a clean, professional stackup PDF with all critical parameters.

A typical export will show the six-layer hybrid example above with each dielectric thickness, Dk, copper weight, and target impedance in a single-page cross-section view. Attach this PDF to your Gerber package and reference it in the fabrication notes—it eliminates ambiguity and reduces NRE re-spins.

Common Stackup Mistakes in RF Designs

After reviewing thousands of RF fabrication packages, certain errors recur:

• Split ground planes under RF traces: A slot in the reference plane forces return current to detour, creating a slot antenna that radiates and couples to adjacent signals. If a split is unavoidable, stitch it with closely spaced vias (λ/20 spacing at the highest frequency).
• Ignoring solder-mask Dk loading: Standard LPI solder mask has a Dk of roughly 3.3–3.8. Over a microstrip trace, it shifts impedance downward by 2–5 Ω. Either model it or specify bare-copper zones on RF traces in the stackup notes.
• Specifying generic “Rogers” without a part number: RO4003C and RO4350B have different Dk (3.38 vs 3.48), different Df, and different processing requirements. A vague callout forces the fabricator to guess—and they will guess conservatively, often adding cost.
• CTE mismatch in hybrid builds: FR-4 has a Z-axis CTE of roughly 50 ppm/°C above Tg, while PTFE laminates are around 24 ppm/°C. Without matched prepreg or stress-relief features, the board can warp or delaminate during reflow. The stackup design must account for this.
• Missing back-drill callout: Through-hole vias that pass through mmWave signal layers create stubs. At 77 GHz, a 10 mil stub resonates destructively. The stackup must specify back-drill depth and tolerance (typically ±4 mil) for every via that penetrates an RF layer.

Avoiding these errors is a core topic in mmWave PCB design guides, and each one is caught during a proper stackup review before the board ever reaches CAM.

Preparing Your RFQ for a Stackup Review

To get a useful stackup recommendation back quickly, your RFQ should include at minimum:

• Operating frequency range (e.g., 24.0–24.25 GHz)
• Target impedances (50 Ω microstrip, 100 Ω differential stripline, etc.)
• Layer count preference or constraint
• Preferred laminate or “recommend best value”
• Board thickness constraint (if any)
• Quantity and prototype vs. production intent
• Compliance requirements: MIL-PRF-31032, IPC-6012 Class 3, ITAR, medical, etc.

Use the checklist below to verify your RFQ package is complete before submitting. Missing information is the number-one cause of delayed quotes and stackup re-spins.

A complete checklist submission typically receives a preliminary stackup proposal within two business days, including impedance modeling results and a DFM summary. Incomplete submissions may require a follow-up call, adding three to five days to the cycle. Investing ten minutes in the checklist saves a week of iteration.

Stackup Design Workflow: From Concept to CAM

1. Define requirements: Frequency, impedance targets, layer count, compliance class.
2. Select materials: Match Dk/Df to frequency band; choose hybrid or uniform construction.
3. Model impedance: Run a 2D field solver (Polar Si9000 or equivalent) on the proposed cross-section. Iterate dielectric thickness and trace width until targets are met within ±5 % at the design frequency.
4. Check DFM: Verify minimum trace/space, via aspect ratio, back-drill feasibility, and registration tolerance are within the fabricator’s process window.
5. Generate stackup document: Cross-section drawing, impedance table, material callouts, DFM notes.
6. Review with fabricator: The fabricator confirms material availability, lamination sequence, and any process adders.
7. Release to layout: Import the verified stackup into your EDA tool (Altium layer-stack manager, Cadence Allegro, or KiCad) and set impedance rules accordingly.

When the stackup design service is bundled with the RFQ, steps 2 through 6 happen in parallel with quoting, so the engineer receives a buildable stackup and a firm price at the same time.

Frequently Asked Questions

Can I use FR-4 for RF above 1 GHz?

FR-4 can work up to about 3–4 GHz for short trace runs where 0.02 Df loss is acceptable. Above that, insertion loss and Dk variation with frequency degrade performance quickly. Mid-Dk laminates like Megtron 6 bridge the gap to about 20 GHz; beyond that, PTFE-based materials are standard.

How many layers does a typical RF board need?

Two layers suffice for simple single-band front-ends. Four layers are the most common for designs combining RF and moderate digital. Six to eight layers appear in radar, phased-array and multi-band systems that need buried stripline isolation and separate power distribution.

What impedance tolerance should I specify?

±10 % is standard for production RF boards per IPC-6012 Class 2. For mmWave designs above 40 GHz or tightly coupled filter structures, ±7 % or ±5 % may be needed, but this requires tighter dielectric-thickness and etch-profile control—discuss with the fabricator during stackup review.

Does solder mask affect RF performance?

Yes. LPI solder mask (Dk ≈ 3.3–3.8) over a microstrip line shifts impedance downward and adds dielectric loss. Common practice is to open the mask over critical RF traces, or to model the mask as a dielectric layer in the impedance solver.

What is the benefit of getting a stackup review with my RFQ?

A bundled stackup review ensures the quoted price reflects actual materials and process steps, eliminates surprises at CAM review, and gives you a version-controlled stackup document you can import directly into your EDA tool—saving one to two design iterations on average.