RF Cavity PCB: Embedded Component Cavity Design

What Is an RF Cavity PCB?

An RF cavity PCB is a multilayer board that contains one or more precision pockets—cavities—milled into the laminate stackup so that active or passive components sit partially or fully below the board surface. By placing an MMIC die, bare-die LNA, or chip resistor directly against an internal copper plane, the designer shortens the electrical path to the ground reference, cuts wire-bond or ribbon-bond loop inductance by 60–80%, and opens a direct thermal conduction path to a heatsink or chassis. Cavity construction is standard practice in radar T/R modules, satellite transponders, electronic warfare receivers, and 5G mmWave front-end modules operating above 20 GHz.

Why Use a Cavity Instead of Surface Mount?

At frequencies above roughly 10 GHz, every tenth of a millimeter of bond-wire length adds measurable parasitic inductance—about 0.8–1.0 nH per millimeter of wire in free space. A conventional surface-mount MMIC sitting on top of the board needs a longer wire bond down to the trace layer, introducing series inductance that degrades gain flatness and shifts matching networks. Dropping the die into a cavity that is flush with the signal layer shrinks that bond to under 0.3 mm, keeping parasitic inductance below 0.3 nH.

Thermal performance improves in parallel. A GaAs or GaN die dissipating 2–5 W can be epoxy-attached or solder-attached directly to an exposed copper coin or a thick internal copper plane at the cavity floor. The thermal resistance from junction to heatsink drops significantly compared with conducting heat through multiple dielectric layers. For power amplifiers in automotive-grade RF PCBs, this can be the difference between meeting and failing AEC-Q100 junction-temperature limits.

Cavity Types and How They Are Made

Top-Side Open Cavity (Most Common)

Material is removed from the component side down to a target internal layer. The floor of the cavity is usually a copper plane or a copper coin press-fitted into the stackup. Depth-controlled mechanical routing with a Z-axis accuracy of ±50 µm (±2 mil) is the standard method. For tighter tolerances, some fabricators use laser ablation to stop on a copper reference layer with ±25 µm accuracy.

Bottom-Side Cavity

Used when the component must face a chassis or cold plate. The board is flipped during assembly, and the die is bonded into a pocket on the back side. This approach is common in space-grade RF PCBs where conducted cooling through a metal housing is the only thermal path.

Through Cavity (Window)

The pocket goes all the way through the board, and the component is supported by a separate carrier or pedestal below. Through cavities simplify routing but require a secondary mechanical structure and careful sealing if hermeticity matters.

Stepped Cavity

Two or more depth levels within a single pocket, typically one shelf for wire-bond pads and a deeper floor for the die attach. Stepped cavities demand two separate routing passes, each with its own depth setting, and the depth tolerance at each step must be independently verified.

Stackup Considerations for Cavity PCBs

Cavity depth is set by the stackup, not the other way around. The designer must decide which internal copper layer will serve as the cavity floor, then build the layer count and dielectric thicknesses to place that floor at the right depth for the component. A GaAs MMIC that is 100 µm (4 mil) thick, for example, needs the cavity floor positioned so the die surface ends up coplanar with the signal trace layer—meaning the cavity depth equals the total dielectric and copper thickness above the floor layer minus the die thickness.

Working with an RF PCB stackup design service early in the project avoids the common mistake of finalizing the stackup for impedance and then discovering the cavity depth is mechanically impractical. Key stackup rules for cavity boards:

• Minimum floor thickness: At least 0.2 mm (8 mil) of dielectric plus copper must remain below the cavity floor to maintain structural integrity during routing and assembly.
• Copper coin option: A press-fit copper slug (coin) laminated into the stackup provides a flat, thermally excellent floor. Coins are typically 1.0–2.0 mm thick, CTE-matched to the die material where possible.
• Bonded PTFE layers: If the board uses multilayer PTFE construction, the bond-ply resin flow during lamination must be controlled so it does not fill the pre-routed cavity area. Some fabricators route cavities after lamination to avoid this issue.
• Symmetry: Removing material from one side of the stackup creates a stress imbalance. Mirror the cavity with a copper relief or balancing cavity on the opposite side to prevent warpage, especially on boards thinner than 1.6 mm.

Surface Finish Inside the Cavity

The cavity floor finish must be compatible with the die-attach process. Conductive epoxy attach works on most finishes, but eutectic solder attach (AuSn at 280 °C) demands a gold surface. Wire-bondable gold plating with a minimum of 1.27 µm (50 µin) of 99.99% pure gold over a nickel or palladium barrier is the standard for cavities that will receive aluminum or gold wire bonds. Outside the cavity, the rest of the board can use a different, lower-cost finish—ENIG for signal pads, for instance—since selective plating is routine on cavity boards.

Component Derating in Cavity Environments

Embedding a component in a cavity improves thermal conduction to the floor but also restricts convective airflow around the device. For components that rely partly on top-side convection—voltage regulators, driver amplifiers—the reduced airflow means the effective thermal resistance junction-to-ambient (θ_JA) can be higher than the datasheet value. Apply a derating factor to the maximum power dissipation to account for the enclosed environment. A conservative starting point is 20–30% power derating for fully enclosed cavities with no forced air, dropping to 10% if the cavity is open-topped with a direct thermal coin to a heatsink.

Use the calculator below to check whether your component’s derated power stays within safe limits for the cavity thermal environment. Enter the component’s rated power, the ambient temperature, and the maximum junction temperature from the datasheet.

If the calculator shows the derated power is less than your actual dissipation, you have two options: increase the copper coin area to lower thermal resistance, or add a thermally conductive lid (aluminum or copper) epoxied over the cavity to conduct heat upward to a heatsink. In either case, verify with a thermal simulation before committing to fabrication.

Component Orientation and Placement Verification

Cavity assembly is less forgiving than standard SMT because rework inside a pocket is difficult or impossible without damaging adjacent wire bonds. Die orientation—polarity, gate-drain alignment, and ground-paddle registration—must be verified before epoxy cure. The confined space also means pick-and-place nozzles need custom tips, and visual inspection cameras must focus at a different Z-height than the rest of the board.

Before releasing Gerber and assembly data, run your cavity component orientations through a verification check. Confirm that pin-1 indicators, thermal-pad orientations, and polarity marks are consistent between your schematic, layout, and assembly drawing.

A single reversed MMIC in a cavity typically means scrapping the board, since rework heat can delaminate the cavity floor or lift adjacent traces. Catching orientation errors at the design-review stage is the cheapest insurance available.

Design Rules and Fabrication Tolerances

Cavity PCBs require additional drawing callouts beyond standard RF board notes. The fabrication drawing should specify:

1. Cavity depth referenced to the board surface, with tolerance (e.g., 0.60 mm ±0.05 mm from top surface).
2. Floor layer identified by layer number (e.g., “Route to expose Layer 4 copper”).
3. Corner radii—mechanical routing leaves a minimum inside corner radius equal to half the cutter diameter, typically 0.4–0.5 mm. Laser-routed cavities can achieve sharper corners.
4. Keep-out zone around the cavity edge: minimum 0.5 mm from any via or trace to the cavity wall to prevent delamination.
5. Floor flatness requirement, usually ≤25 µm across the die-attach area, critical for void-free solder attach per IPC-6012 Class 3/A requirements.

For rapid iteration on cavity designs, quick-turn RF PCB prototyping with cavity capability lets you validate depth accuracy and assembly fit in 5–7 days before committing to volume tooling.

Common Pitfalls and How to Avoid Them

• Resin smear on cavity floor: Routing after lamination can smear epoxy onto the copper floor, degrading solder or epoxy adhesion. Specify a plasma desmear or micro-etch step for the cavity floor in your fabrication notes.
• Delamination at cavity edges: The abrupt transition from full stackup to reduced stackup creates stress concentration. Radiused corners and a minimum 0.5 mm standoff from the nearest via reduce risk.
• CTE mismatch cracking: A GaAs die (CTE ~5.7 ppm/°C) bonded to a bare copper floor (CTE ~17 ppm/°C) will stress the bond line during thermal cycling. Use a CTE-matched carrier (CuMo, CuW) or a compliant die-attach adhesive rated for the expected temperature range.
• Solder mask bridging: Solder mask applied over the cavity edge can wick into the pocket during curing. Define a mask-free zone extending 0.25 mm inside the cavity wall. Consult RF solder mask options for Dk impact if mask is needed near signal traces at the cavity rim.

Material Selection for Cavity RF PCBs

Not every laminate machines cleanly into a cavity. PTFE-based materials like Rogers RO4350B (Dk 3.48, Df 0.0037 at 10 GHz) route well because the thermoset resin system is rigid and produces clean edges. Pure PTFE laminates (RT/duroid 5880, Dk 2.20) are softer and can smear or deform during mechanical routing; laser ablation or cryogenic routing may be needed. Hydrocarbon ceramic laminates and standard FR-4 core layers used in hybrid stackups also cavity-route cleanly.

When a Cavity Is Not the Right Answer

Cavities add cost—typically 15–30% over a flat board of the same layer count—because of the extra routing pass, tighter inspection, and selective plating. If the frequency is below 10 GHz, surface-mount components with short, well-modeled leads often perform adequately without a cavity. Similarly, if thermal dissipation is under 0.5 W per device, thermal vias to a back-side pad may be sufficient. Reserve cavities for bare-die attach, wire-bond interconnects, or situations where the parasitic budget is measured in tenths of a nanohenry.

Frequently Asked Questions

What is the typical depth tolerance for an RF cavity PCB?

Mechanical depth-controlled routing achieves ±50 µm (±2 mil). Laser ablation stopping on a copper reference layer tightens this to ±25 µm. Always specify depth as a dimension from the board surface with a bilateral tolerance.

Can I put a cavity in a standard FR-4 board?

Yes. FR-4 machines cleanly and cavities in FR-4 are common for embedded passives and low-frequency die attach. For RF performance above a few GHz, the cavity floor and surrounding signal layers should use a low-loss laminate even if FR-4 is used elsewhere in the stackup.

How do I ensure coplanarity between the die surface and the trace layer?

Calculate cavity depth as: total stackup thickness above the floor layer minus the component height (die + die-attach adhesive thickness). Include the adhesive bond-line thickness (typically 15–25 µm for conductive epoxy) in the calculation. Verify with a first-article measurement using a profilometer or optical inspection per IPC-A-610 coplanarity criteria.

Does a cavity affect controlled impedance on nearby traces?

Traces routed on the same layer as the cavity rim lose their reference plane where the dielectric has been removed. Keep controlled-impedance traces at least 1.0 mm (40 mil) from the cavity edge, or route them on an internal layer that is unaffected by the pocket.

What surface finish is best inside an RF cavity?

For wire-bonding, electrolytic soft gold (≥1.27 µm) over nickel or palladium is required. For conductive-epoxy die attach without wire bonds, ENIG or ENEPIG is acceptable and less expensive. The choice depends on the interconnect method, not the cavity itself.