Introduction to High Speed PCB Design and Topology

Printed circuit board (PCB) design for high speed applications requires careful consideration of the layout topology to ensure signal integrity, minimize noise and crosstalk, and achieve target performance. As digital systems push to ever higher frequencies and data rates, the PCB layout becomes a critical factor in the success of the design.

This article will dive into the key aspects of high speed PCB layout topology, including:

• Signal routing and trace geometry
• Power distribution networks
• Grounding and shielding techniques
• Component placement
• Simulation and analysis

By understanding and applying best practices in each of these areas, designers can create robust, high-performance PCBs for demanding high speed applications.

Signal Routing and Trace Geometry

The routing of high speed signals is one of the most important aspects of PCB topology. At GHz frequencies, the PCB traces behave like transmission lines and must be designed to maintain controlled impedance and minimize signal reflections.

Microstrip vs Stripline Routing

There are two main types of PCB transmission lines:

1. Microstrip – the signal trace is routed on the outer layer of the PCB, with a reference plane (usually ground) on the adjacent inner layer. Microstrips are easier to route but more susceptible to external noise.

2. Stripline – the signal trace is routed on an inner layer, with reference planes above and below. Striplines provide better shielding but complicate the layout.

The choice between microstrip and stripline depends on factors like the available board layers, the noise environment, and the density of high speed traces.

Trace Width and Impedance Control

To maintain signal integrity, high speed traces must have a controlled characteristic impedance, typically 50Ω for single-ended signals and 100Ω for differential pairs. The trace geometry (width and thickness) and the PCB Stackup (dielectric height and constant) determine the impedance.

Trace width calculators are used to determine the required width for a given stackup and target impedance. For example:

Impedance	Dielectric Thickness	Trace Thickness	Trace Width
50Ω	5 mil	1.4 mil	15 mil
100Ω diff	5 mil	1.4 mil	6 mil

Consistent impedance requires a uniform trace width, so high speed traces should avoid sharp corners and should taper gradually when changing width.

Length Matching and Delay Tuning

In addition to impedance control, high speed traces often require length matching to ensure equal propagation delays. This is especially important for differential pairs, parallel buses, and synchronous interfaces.

The goal is to match the electrical length of the traces, which depends on the actual (“manhattan”) length and the propagation velocity in the dielectric material. Trace length calculators can determine the maximum length mismatch based on the edge rate and timing requirements.

Length matching is done by adding serpentine delay sections to the shorter traces. The serpentines should use smooth curves (typically 45° bends) to avoid impedance discontinuities.

Power Distribution Network (PDN) Design

A clean, stable power supply is essential for high speed circuits to operate correctly. The power distribution network on the PCB must provide a low impedance path from the voltage regulator to the ICs, and minimize transient voltage ripple and noise.

PDN Impedance

The target impedance of the PDN depends on the current draw and transient response of the ICs. As a general rule, the PDN impedance should be kept below 100 mΩ up to the GHz range.

Achieving this requires careful design of the PCB stackup and power/ground planes. Some key factors are:

• Using thin dielectrics between the power and ground layers to increase interplane capacitance
• Adding more power and ground layers to decrease the spreading inductance
• Placing decoupling capacitors close to the ICs to shunt high frequency transients

The PDN impedance can be modeled and simulated using specialized tools to validate the design.

Decoupling and Bypass Capacitors

Decoupling capacitors are a critical part of the PDN, serving to locally store charge and filter high frequency noise. They should be placed as close as possible to the power pins of the ICs.

The value and placement of the decoupling capacitors is chosen to optimize the PDN impedance across the required frequency range, typically using a mix of bulk (μF), ceramic (nF), and small case size (pF) capacitors in parallel.

General guidelines for decoupling include:

• Use at least one capacitor per power pin, placed on the same side of the PCB
• Place bulk capacitors near the voltage regulator output
• Use controlled-ESR capacitors for best high frequency performance
• Orient capacitors to minimize the loop area with the power/ground planes

Bypass capacitors are used to shunt noise between sensitive analog and digital sections of the PCB. They should be placed at the boundary between the sections, with a separate analog ground plane.

Grounding and Shielding Techniques

Proper grounding and shielding are essential to minimize noise coupling and interference in high speed PCBs. The goal is to provide a low impedance return path for the signals and to contain electromagnetic fields.

Ground Planes and Stitching Vias

Solid ground planes are used to provide a continuous return path for the high speed signals. They also serve as a shield to contain radiated fields.

On multi-layer PCBs, the ground planes should be stitched together with vias to ensure a low impedance connection. The via spacing should be less than λ/10 at the highest frequency of interest.

For mixed-signal designs, separate analog and digital ground planes are often used to prevent noise coupling. They are joined at a single point, typically near the analog-to-digital converter (ADC).

Shielding and Isolation

Sensitive circuits should be shielded from sources of electromagnetic interference (EMI) such as high speed digital traces, switching power supplies, and RF modules.

Shielding techniques include:

• Metal shielding cans over sensitive components
• Gridded ground shields between layers
• Guard traces and copper pours around sensitive traces
• Avoiding routing high speed traces over breaks in the ground plane

Isolation techniques are used to prevent coupling between different sections of the PCB. These include:

• Separating analog and digital sections with a ground moat
• Placing sensitive traces on opposite sides of the board from noisy traces
• Using ferrite beads and common mode chokes on I/O lines
• Routing high speed traces perpendicular to each other to minimize crosstalk

Component Placement and Routing

The placement and routing of components on a high speed PCB can have a significant impact on signal integrity and EMC performance.

Component Placement Guidelines

Components should be placed to minimize the length of high speed traces and to facilitate routing. Guidelines include:

• Placing ICs close to their associated connectors and components
• Orienting ICs to minimize the number of layer transitions
• Grouping components by function and speed to minimize trace lengths
• Placing decoupling capacitors close to IC power pins
• Separating analog and digital components to minimize coupling
• Placing tall components like electrolytic capacitors and connectors near the board edge

For ball grid array (BGA) packages, the escape routing and breakout pattern should be optimized for signal integrity. This typically involves using diagonal traces to maximize the distance between balls.

High Speed Routing Techniques

Once the components are placed, the high speed traces must be routed to minimize length, avoid impedance discontinuities, and control crosstalk.

Key routing techniques include:

• Routing critical traces first, using the most direct path
• Avoiding vias on high speed traces if possible, or using microvias and via stubs
• Minimizing the number of reference plane transitions
• Using rounded corners and smooth bends to avoid impedance discontinuities
• Avoiding stubs and unterminated traces that can cause reflections
• Spacing traces to control crosstalk, using 3W rule of thumb for microstrips
• Routing differential pairs together with a constant spacing
• Avoiding splitting differential pairs around obstacles or vias
• Using stitching vias and copper pours to provide a continuous return path
• Placing ground vias near connectors and component pins to reduce ground bounce

By following these placement and routing guidelines, designers can create PCBs that are optimized for high speed performance.

Simulation and Analysis

Simulation and analysis tools are essential for validating the high speed PCB design before fabrication. They can help identify signal integrity issues, EMI/EMC problems, and thermal hotspots.

Signal Integrity Simulation

Signal integrity (SI) simulation predicts the quality of the high speed signals as they propagate through the PCB interconnects. It takes into account factors like:

• Trace impedance and discontinuities
• Crosstalk and coupling
• Reflections and ringing
• Attenuation and dispersion
• Jitter and eye closure

SI simulation tools include:

• SPICE-based circuit simulators for pre-layout analysis
• 3D full-wave electromagnetic solvers for post-layout extraction
• Statistical simulation for advanced signaling like DDR and SerDes

The goal is to ensure that the signals meet the required specifications for rise/fall time, overshoot, undershoot, and timing.

Power Integrity Analysis

Power integrity (PI) analysis predicts the quality of the power supply voltage as it is distributed across the PDN. It takes into account factors like:

• PDN impedance vs frequency
• Transient current draw and voltage ripple
• Decoupling capacitor placement and values
• Voltage drop due to IR losses

PI analysis tools include:

• Frequency domain solvers for AC impedance
• Time domain solvers for transient response
• Integrated SI/PI co-simulation

The goal is to ensure that the PDN impedance is sufficiently low and that the voltage ripple is within acceptable limits.

EMI/EMC Analysis

Electromagnetic interference (EMI) and electromagnetic compatibility (EMC) analysis predicts the radiated and conducted emissions from the PCB and the susceptibility to external interference.

EMI/EMC analysis tools include:

• 3D full-wave solvers for far-field radiation patterns
• Transmission line and lumped element models for conducted emissions
• Finite element method (FEM) and method of moments (MoM) solvers
• Shielding effectiveness and coupling path analysis

The goal is to ensure that the PCB meets the relevant EMC standards and does not interfere with other systems.

Thermal Analysis

Thermal analysis predicts the temperature distribution on the PCB and identifies potential hotspots that could affect reliability.

Thermal analysis tools include:

• Finite element method (FEM) solvers for steady-state and transient analysis
• Computational fluid dynamics (CFD) for airflow and cooling
• Thermal network models for rapid estimation

The goal is to ensure that the PCB operates within the safe temperature limits for the components and materials.

By using these simulation and analysis tools throughout the design process, high speed PCB designers can identify and correct problems early, reducing the risk of costly redesigns and improving the overall performance and reliability of the final product.

FAQ

Q: What is the most important factor in high speed PCB layout?

A: Signal integrity is the most critical factor in high speed PCB layout. This means ensuring that the high speed signals maintain their shape and timing as they propagate through the interconnects, without excessive distortion, attenuation, or crosstalk.

Q: How do you control impedance in high speed traces?

A: Impedance is controlled by the geometry of the traces (width, thickness, and spacing) and the properties of the PCB stackup (dielectric constant and height). Trace width calculators are used to determine the required width for a given stackup and target impedance, typically 50Ω for single-ended traces and 100Ω for differential pairs.

Q: What is the purpose of decoupling capacitors?

A: Decoupling capacitors serve to locally store charge and filter high frequency noise on the power supply rails. They should be placed as close as possible to the power pins of the ICs, with a value and placement chosen to optimize the PDN impedance across the required frequency range.

Q: How do you prevent crosstalk between high speed traces?

A: Crosstalk can be minimized by increasing the spacing between traces, typically using the 3W rule (three times the trace width) for microstrip traces. Other techniques include routing sensitive traces on different layers, using guard traces or ground pours, and routing traces perpendicular to each other.

Q: What types of simulation are used for high speed PCB design?

A: Signal integrity, power integrity, EMI/EMC, and thermal simulations are commonly used for high speed PCB design. These simulations help predict the quality of the signals and power supply, the electromagnetic emissions and susceptibility, and the temperature distribution on the PCB. By identifying problems early, simulations can reduce the risk of costly redesigns and improve the overall performance and reliability of the final product.

Conclusion

High speed PCB layout is a complex and critical aspect of modern electronic design. By understanding the key principles of signal integrity, power distribution, grounding and shielding, component placement, and simulation, designers can create PCBs that are optimized for high speed performance.

While there is no one-size-fits-all approach to high speed layout, following best practices and using the right tools can help ensure a successful design. By paying attention to the details of the PCB topology, designers can minimize the risk of signal integrity issues, EMI/EMC problems, and thermal hotspots, and create products that meet the ever-increasing demands of high speed applications.